Samsung Electronics Co., Ltd.

SukYong Kang

Hun-Dae Choi

Han-gi Jung

Hye-Seung Yu

Won-Joo Yun

Jae-Hun Jung

Hangi Jung

Hyunui Lee

Hyun-Ui Lee

A semiconductor device includes a decoder configured to receive an extended mode register set (EMRS) code including specific information, and decode the received EMRS code to acquire the specific information; a peripheral controller configured to generate a control signal based on the specific information; and a peripheral region including a plurality of buffers, the plurality of buffers being configured to be controlled by the control signal, wherein the specific information includes information indicating an expected bandwidth of input data that is to be input to one of the plurality of buffers.

Semiconductor device

Disclosed are a method and a device for detecting a short circuit between adjacent micro-bumps. The method includes setting outputs of a pull-up driver and a pull-down driver of a data output circuit connected with a micro-bump to be suitable for a test type and determining whether a short circuit is generated.

Short circuit detecting device of stacked memory chips and method thereof

A memory device including a command window generator is provided. The command window generator is configured to generate a delay signal by converting a delay time between a clock signal input to a write path circuit and a clock signal output to a write path replica circuit into a number of cycles of an internal clock signal, by using the write path circuit and the write path replica circuit, and generate a command window to correspond to a data window using the delay signal. The delay window may correspond to a burst length of write data.

Memory device having command window generator

A memory module includes a first memory device including a first one-die termination circuit for impedance matching of a signal path and a second memory device sharing the signal path with the first memory device and including a second on-die termination circuit for impedance matching of the signal path, wherein the signal path corresponds to a command or address signal path provided from a host, and the first and second on-die termination circuits are individually controlled according to control of the host.

Memory module including on-die termination circuit and control method thereof

An input-output circuit includes a reception circuit and a register circuit. The reception circuit operates in accordance with a normal write protocol commonly in a normal write mode and a test write mode. The reception circuit receives a plurality of input signals to generate a plurality of latch signals. The register circuit generates a plurality of test result signals based on the latch signals in the test write mode. The input-output circuit may perform the multiple-input shift register (MISR) function in accordance with the normal write path and the normal write protocol. The MISR function may be performed efficiently without consideration of additional timing adjustment for the test write operation because the MISR function is performed under the same timing condition as the normal write operation.

Input-output circuit for supporting multiple-input shift register (MISR) function and memory device including the same

Provided are a reference voltage training device and a method thereof. The reference voltage training device includes a comparator configured to compare a toggle signal with a reference voltage and output a comparison signal, a duty cycle detector configured to check a duty ratio of the comparison signal, and a reference voltage level changing unit configured to fix the reference voltage when the duty ratio meets a predetermined condition and to change a level of the reference voltage when the duty ratio does not meet the predetermined condition. The comparator outputs a changed comparison signal using the changed reference voltage.

Reference voltage training device and method thereof

A semiconductor device may include a termination resistor circuit including a first termination resistor connected to a power voltage and a second termination resistor between the first termination resistor and a ground, a value of the first termination resistor and the second termination resistor changes based on a feedback signal; a mismatch detector may generate a compared result based on a potential difference between a voltage of a center node, between the first and second termination resistors, and a reference voltage; a code generator may generate the feedback signal based on the compared result, and generate a feedback code based on the compared result; a code register may generate a mismatch code controlling a mismatch between the first and second termination resistors based on the feedback code; and a corrector may compensate for the mismatch between the first and second termination resistors based on the mismatch code.

Growing community of inventors

Suwon-si, South Korea

SukYong Kang