Samsung Electronics Co., Ltd.

Sukki Yoon

Heesung Chae

Yunhwan Jung

Kyung-Min Kim

Sunyool Kang

Yongjun Cho

Jaeyoung Bae

Kyungmin Kim

Kyungtae Kim

Haesick Sul

An image sensor, including a pixel array including a plurality of pixels connected to row lines extending in a first direction and column lines extending in a second direction intersecting the first direction; a ramp voltage generator configured to output a ramp voltage; a sampling circuit including a plurality of comparators, each comparator of the plurality of comparators having a first input terminal connected to a column of the column lines and a second input terminal configured to receive the ramp voltage; and an analog-to-digital converter configured to convert an output of the plurality of comparators to a digital signal, wherein the plurality of comparators include a first comparator connected to a first column line, and a second comparator connected to a second column line adjacent to the first column line in the first direction, wherein each of the first comparator and the second comparator includes a first transistor and a second transistor disposed sequentially in the second direction, and wherein a gap between the first transistor of the first comparator and the second transistor of the first comparator is different from a gap between the first transistor of the second comparator and the second transistor of the second comparator.

Image sensor having reduced parasitic capacitance

An image sensor compensates for noise. The image sensor includes a pixel array that includes a common monitor output line, a first monitoring pixel outputting a first monitoring signal, a second monitoring pixel outputting a second monitoring signal, and an active pixel configured to output a sensing signal based on an incident light. The image circuit also includes a binning circuit that receives the first and second monitoring signals through the common monitor output line and generates an average monitoring signal by performing binning on the first and second monitoring signals, and an analog-to-digital converter that detects an alternating current (AC) component of the average monitoring signal and couples the sampled AC component of the average monitoring signal to the sensing signal, thereby compensating for noise.

Image sensor

An electronic circuit is provided. The electronic circuit includes a first current generating circuit configured to output a first operating current based on a first operating voltage; and an input circuit configured to: receive a first current corresponding to a first input voltage and a second current corresponding to a second input voltage, wherein the first current and the second current are based on the first operating current; receive a third current and a fourth current that are generated based on the first operating voltage; and generate a fifth current corresponding to the second input voltage based on a second operating current. The electronic circuit is configured to generate an output voltage that is associated with a difference between the first input voltage and the second input voltage based on the second current, the fourth current and the fifth current, and the fourth current corresponds to the third current.

Electronic circuit for configuring amplifying circuit configured to output voltage including low noise

An image sensor includes a pixel array including pixels that are arranged in a matrix and respectively generate pixel signals, a row driver to drive the plurality of pixels row by row, a timing generator to generate a clock signal and address signals, a column driver to generate a plurality of column selection signals sequentially activated in response to the clock signal and the address signals, and a column array to receive the pixel signals through a plurality of column lines, perform an analog-to-digital conversion on the pixel signals, and sequentially output pixel data values through an output buffer. The column driver may include a clock tree including first delay elements and second delay elements to generate a plurality of delay clock signals, and a decoding circuit to generate the plurality of column selection signals.

Growing community of inventors

Suwon-si, South Korea

Sukki Yoon