Samsung Electronics Co., Ltd.

Sukjin Kim

Chanhee Jeon

Younghwan Park

Kyounghoon Kim

Hansu Cho

Mijin Lee

Seungwon Lee

Hyunjung Kim

Scott Mahlke

Hyunchul Park

Yongjun Park

Heejun Shim

Namho Kim

Keshava Prasad Nagaraja

Dongkwan Suh

Sangyoung Cho

Keshava Prasadnagaraja

An electrostatic discharge clamp circuit includes a resistor connected between a first node and a second node, a first capacitor connected between the second node and a third node, a second capacitor connected between a fourth node and the third node, a third capacitor connected between a fifth node and the third node, a first inverter providing a power supply voltage or a voltage of the fourth node based on a voltage of the second node, a second inverter providing an output voltage of the first inverter or a voltage of the fifth node based on the voltage of the fourth node, a third inverter configured to provide an output voltage of the second inverter or the ground voltage based on the voltage of the fifth node.

Electrostatic discharge clamp circuit

An electrostatic discharge (ESD) device having a small size, a low turn-on voltage, and a low on resistance and an ESD protection circuit including the ESD device are provided. The ESD device includes a well formed in a substrate to have a first conductive type, an active region being defined at an upper portion of the substrate, a plurality of fins extending in a first direction to have a structure protruding from the substrate, a first conductive impurity region formed with first conductive impurities, a second conductive impurity region formed with second conductive impurities, and a fin-cut isolation region disposed between the first conductive impurity region and the second conductive impurity region in the first direction to cut each fin, wherein a bottom surface of the fin-cut isolation region is higher than a bottom surface of the active region.

FinFET ESD device with fin-cut isolation region

A semiconductor device includes first well regions in a substrate and spaced apart from each other, a connection doped region between the first well regions, and a first interconnection line electrically connected to the connection doped region through a first contact. The first well regions and the connection doped region include impurities of a first conductivity type, and a concentration of the impurities in the connection doped region is higher than that in the first well regions. The first well regions extend into the substrate to a depth larger than that of the connection doped region. A first portion of the connection doped region is disposed in the first well regions and a second portion of the connection doped region contacts the substrate.

Semiconductor device

The present disclosure relates to a communication method and system for converging a 5th-Generation (5G) communication system for supporting higher data rates beyond a 4th-Generation (4G) system with a technology for Internet of Things (IoT). The present disclosure may be applied to intelligent services based on the 5G communication technology and the IoT-related technology, such as smart home, smart building, smart city, smart car, connected car, health care, digital education, smart retail, security and safety services. A Processing Element (PE) implemented in an accelerator in a convolutional neural network, which includes a first buffer configured to transfer input data to one other PE, and a second buffer configured to transmit to an outside output data that is processed on the basis of the input data; and an operation unit configured to generate output data.

Accelerator in convolutional neural network and method for operating the same

An electronic apparatus is provided. The electronic apparatus includes a storage storing object data and kernel data, and a processor including a plurality of processing elements arranged in a matrix formation, wherein the processor is configured to input corresponding first elements among a plurality of first elements included in the object data into processing elements arranged in a first row among the plurality of processing elements, and input a plurality of second elements included in the kernel data sequentially into the processing elements arranged in the first row to perform operations between the corresponding first elements and the plurality of second elements, to identify a depth in which a first element and a second element have a non-zero value, and to input the first element and the second element corresponding to the identified depth into a calculator included in each of the processing elements arranged in the first row to perform a convolution operation.

Electronic apparatus and control method thereof

Disclosed is configuration memory access technology in a processor with a reconfigurable architecture. The processor with the reconfigurable architecture includes an array of processing elements (PEs), a configuration memory and a token network. The configuration memory stores configuration data associated with controlling data flow of the respective PEs. The token network reads the configuration data from the configuration memory, estimates data flow of the PEs from the read configuration data, reads required configuration data from the configuration memory based on the estimated data flow, and supplies the required configuration data to corresponding PEs. By reducing configuration memory access frequency through a token network, power consumption may be reduced.

Processor with reconfigurable architecture including a token network simulating processing of processing elements

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Seoul, South Korea

Sukjin Kim