Samsung Electronics Co., Ltd.

Sukhun Choi

Sechung Oh

Jangeun Lee

Junho Jeong

Boun Yoon

Byoungkeun Son

Kyunghyun Kim

Woojin Kim

Kyungtae Nam

Jeongnam Han

Jinho Kim

Hansoo Kim

Sunil Shim

Wonseok Cho

Woo Chang Lim

Jae-Joo Shim

Jae-Jik Baek

Ju-Young Lim

Jaehyoung Choi

Jeahyoung Lee

ChangSup Mun

Injoon Yeo

Youngsoo An

Mingu Kim

Younghyun Kim

Woojin Cho

Sangjine Park

Sang-jun Lee

Inseak Hwang

Byung-Kwon Cho

Doo-Sung Yun

Byoung-Yong Gwak

Myunggeun Song

Mongsup Lee

Woochang Lim

Dae Kyom Kim

Kevin Ahn

KyungTae Nam

Jaeseung Hwang

JungHyeon Kim

Provided is a semiconductor device including a substrate with an active pattern, a gate electrode crossing the active pattern, and a gate capping pattern on the gate electrode. The gate capping pattern may have a width larger than that of the gate electrode, and the gate capping pattern may include extended portions extending toward the substrate and at least partially covering both sidewalls of the gate electrode.

Semiconductor device and method of fabricating the same

A magnetic memory device may include a first vertical magnetic layer, a non-magnetic layer on the first vertical magnetic layer, and a first junction magnetic layer on the non-magnetic layer, with the non-magnetic layer being between the first vertical magnetic layer and the first junction magnetic layer. A tunnel barrier may be on the first junction magnetic layer, with the first junction magnetic layer being between the non-magnetic layer and the tunnel barrier. A second junction magnetic layer may be on the tunnel barrier with the tunnel barrier being between the first and second junction magnetic layers, and a second vertical magnetic layer may be on the second junction magnetic layer with the second junction magnetic layer being between the tunnel barrier and the second vertical magnetic layer.

Magnetic memory devices including magnetic layers separated by tunnel barriers

A method of fabricating semiconductor devices having metal gate electrodes includes forming an insulating layer on a semiconductor substrate having a first region and a second region. The insulating layer is formed to include an interlayer insulating layer and a gate insulation layer. The interlayer insulating layer has first and second grooves respectively disposed in the first and second regions, and the gate insulation layer covers at least bottom surfaces of the first and second grooves. A laminated metal layer is formed on the substrate having the insulating layer. A planarization layer having non-photo sensitivity is formed on the laminated metal layer. The planarization layer in the first region is selectively removed using a dry etching process to expose the laminated metal layer in the first region and to form a planarization layer pattern covering the laminated metal layer in the second region.

Methods of fabricating a semiconductor device including metal gate electrodes

A semiconductor device includes a substrate, a device isolation pattern and a passive circuit element. The device isolation pattern is located on the substrate, delimits an active region of the substrate, and includes a recessed portion having a bottom surface located below a plane coincident with a surface of the active region. The passive circuit element is situated in the recess so as to be disposed on the bottom surface of the recessed portion of the device isolation pattern.

Semiconductor devices having passive element in recessed portion of device isolation pattern and methods of fabricating the same

Methods of fabricating semiconductor devices are provided including forming a dielectric interlayer on a substrate, the dielectric interlayer defining an opening therein. A metal pattern is formed in the opening. An oxidization process is performed on the metal pattern to form a conductive metal oxide pattern, and the conductive metal oxide pattern is planarized. Related semiconductor devices are also provided.

Semiconductor devices having metal oxide patterns

A semiconductor memory device includes a substantially planar substrate; a memory string vertical to the substrate, the memory string comprising a plurality of storage cells; and a plurality of elongated word lines, each word line including a first portion substantially parallel to the substrate and connected to the memory string and a second portion substantially inclined relative to the substrate and extending above the substrate, wherein a first group of the plurality of word lines are electrically connected to first conductive lines disposed at a first side of the memory string, and a second group of the plurality of word lines are electrically connected to second conductive lines disposed at a second side of the memory string.

Semiconductor memory device comprising three-dimensional memory cell array

According to a method of fabricating the semiconductor memory device, a contact plug can be protected while mold openings are formed. A semiconductor memory device may include a mold dielectric layer on an entire surface of a substrate, the substrate including a first region and a second region. A contact plug may be provided in a contact hole formed through the mold dielectric layer in the first region. A variable resistor may be provided in a mold opening formed through the mold dielectric layer in the second region. An upper surface of the contact plug may be at a level equal to or lower than an upper surface of the mold dielectric layer.

Semiconductor memory devices having variable resistor and methods of fabricating the same

The present disclosure describes methods of fabricating a semiconductor device. An exemplary method includes forming a metal pattern on a substrate and etching the metal pattern using an etchant including at least an alkaline solution and an oxidant to form a metal electrode, where at least a portion of the surface of the metal electrode is uneven.

Methods of fabricating a semiconductor device having metallic storage nodes

A magnetic memory device includes a magnetic pattern, a reference pattern, a tunnel barrier pattern interposed between the magnetic pattern and the reference pattern, and at least one magnetic segment disposed inside the magnetic pattern. The magnetic segment(s) is/are of magnetic material whose direction of magnetization has at least a component which lies in a plane perpendicular to the magnetization direction of the magnetic pattern.

Magnetic memory devices

Provided are a three dimensional semiconductor memory device and a method of fabricating the same. The method includes forming a stepwise structure by using mask patterns and a sacrificial mask pattern formed on the mask patterns as a consumable etch mask.

Three dimensional semiconductor memory device and method of fabricating the same

Methods of fabricating semiconductor devices

A magnetic memory device includes a magnetic tunnel junction (MTJ) structure and an electrode embedded in a dielectric structure. The MTJ structure includes a free layer. The electrode is formed of silicon-germanium and is electrically connected to the MTJ. The electrode heats the free layer to reduce the coercive force of the free layer to reduce a critical current density.

Magnetic memory device

A semiconductor memory device includes a substantially planar substrate, a memory string vertical to the substrate, the memory string comprising a plurality of storage cells, and a plurality of elongated word lines, each word line including a first portion substantially parallel to the substrate and connected to the memory string and a second portion substantially inclined relative to the substrate and extending above the substrate, wherein a first group of the plurality of word lines are electrically connected to first conductive lines disposed at a first side of the memory string, and a second group of the plurality of word lines are electrically connected to second conductive lines disposed at a second side of the memory string.

Growing community of inventors

Suwon-si, South Korea

Sukhun Choi