Samsung Electronics Co., Ltd.

Sukhan Lee

Shinhaeng Kang

Namsung Kim

Seongil O

Kyomin Sohn

Hak-Soo Yu

Youngcheon Kwon

In Young Lee

Jaeyoun Youn

Jideog Kim

Kijun Lee

Hak-soo Yu

Sungrae Kim

Jaewon Park

Haesuk Lee

Yesin Ryu

Yeonggeol Song

Sanghyuk Kwon

Sunggi Ahn

Hyunsung Shin

Hweesoo Kim

A memory device includes a memory bank including one or more bank arrays, a PIM circuit configured to perform an operation logic processing operation, and an instruction memory including first to minstruction queue segments configured in a circular instruction queue to store instructions provided by a host, where instructions stored in the first to minstruction queue segments are executed in response to an operation request from the host and each new instruction provided by the host is written over a completely executed instruction in the circular instruction queue.

Memory device and method including processor-in-memory with circular instruction memory queue

A memory device for reducing timing parameters and power consumption for an internal processing operation and a method of implementing the same are provided. The memory device includes a memory cell array, a processing-in-memory (PIM) circuit configured to perform a processing operation and a control logic circuit configured to control a normal mode and an internal processing mode. The control logic circuit writes an operation result obtained by the processing operation of the PIM circuit in the internal processing mode in the memory cell array and provides read data read from the memory cell array to the PIM circuit.

Memory device for reducing timing parameters and power consumption for internal processing operation and method of implementing the same

Provided is a memory device including a cell array, a peripheral circuit configured to control a memory operation of the plurality of memory cells, a test logic circuit configured to operate in a test mode and configured to perform a test operation on the plurality of memory cells, a first regulator configured to regulate a first power supply voltage received through a first pad and provide the first power supply voltage to at least one of the cell array and the peripheral circuit, and a power manager between the first pad and an input terminal of the first regulator, and between the first pad and the test logic circuit and configured to provide a test power supply voltage to the test logic circuit. In the test mode, while a first target voltage level of the first regulator fluctuates, a second target voltage level of the power manager is maintained constant.

Memory device and test method of memory device

A memory device supporting a processing-in-memory (PIM) protocol includes a mode register set (MRS) configured to store a first parameter code and a second parameter code regarding the PIM protocol in a first register and a second register, respectively. The first parameter code includes a PIM protocol change code indicating whether a PIM protocol change related to an old version PIM protocol is supported, and the second parameter code includes a PIM protocol code for setting a current operation PIM protocol from among a plurality of PIM protocols. The memory device further includes a PIM circuit configured to perform an internal processing operation based on the current operation PIM protocol.

Backward compatible processing-in-memory (PIM) protocol

A memory device includes a memory having a memory bank, a processor in memory (PIM) circuit, and control logic. The PIM circuit includes instruction memory storing at least one instruction provided from a host. The PIM circuit is configured to process an operation using data provided by the host or data read from the memory bank and to store at least one instruction provided by the host. The control logic is configured to decode a command/address received from the host to generate a decoding result and to perform a control operation so that one of i) a memory operation on the memory bank is performed and ii) the PIM circuit performs a processing operation, based on the decoding result. A counting value of a program counter instructing a position of the instruction memory is controlled in response to the command/address instructing the processing operation be performed.

Memory device for processing operation, data processing system including the same, and method of operating the memory device

A memory device includes a memory cell array, signal lines, a mode selector circuit, a command converter circuit, and an internal processor. The memory cell array includes first and second memory regions. The mode selector circuit is configured to generate a processing mode selection signal for controlling the memory device to enter an internal processing mode based on the address received together with the command. The command converter circuit is configured to convert the received command into an internal processing operation command in response to activation of the internal processing mode selection signal. The internal processor is configured to perform an internal processing operation on the first memory region in response to the internal processing operation command, in the internal processing mode.

Method of performing internal processing operations with pre-defined protocol interface of memory device

A memory device includes a memory bank including a plurality of banks that comprise memory cells, and a PIM (processing in memory) circuit including a plurality of PIM blocks, each of the PIM blocks including an arithmetic logic unit (ALU) configured to perform an arithmetic operation using internal data acquired from at least one of the plurality of banks or an address generating unit. The plurality of PIM blocks include a first PIM block allocated to at least one first bank and a second PIM block allocated to at least one second bank. The address generating unit of the first PIM block is configured to generate a first internal row address for the at least one first bank, and the address generating unit of the second PIM block is configured to generate a second internal row address for the at least one second bank.

Memory device

A processor-implemented includes receiving a first floating point operand and a second floating point operand, each having an n-bit format comprising a sign field, an exponent field, and a significand field, normalizing a binary value obtained by performing arithmetic operations for fields corresponding to each other in the first and second floating point operands for an n-bit multiplication operation, determining whether the normalized binary value is a number that is representable in the n-bit format or an extended normal number that is not representable in the n-bit format, according to a result of the determining, encoding the normalized binary value using an extension bit format in which an extension pin identifying whether the normalized binary value is the extended normal number is added to the n-bit format, and outputting the encoded binary value using the extended bit format, as a result of the n-bit multiplication operation.

Method and apparatus with floating point processing

A processing in memory (PIM) device includes a memory configured to receive data through a first path from a host processor provided outside the PIM device, and an information gatherer configured to receive the data through a second path connected to the first path when the data is transferred to the memory via the first path, and to generate information by processing the data received through the second path.

PIM device, computing system including the PIM device, and operating method of the PIM device

A memory device including: a plurality of pins for receiving control signals from an external device; a first bank having first memory cells, wherein the first bank is activated in a first operation mode and a second operation mode; a second bank having second memory cells, wherein the second bank is deactivated in the first operation mode and activated in the second operation mode; a processing unit configured to perform an operation on first data, output from the first memory cells, and second data, output from the second memory cells, in the second operation mode; and a processing-in-memory (PIM) mode controller configured to select mode information, indicating one of the first operation mode and the second operation mode, in response to the control signals and to control at least one memory parameter, at least one mode register set (MRS) value, or a refresh mode according to the mode information.

Memory device, a controller for controlling the same, a memory system including the same, and a method of operating the same

A semiconductor memory device includes a buffer die and a plurality of memory dies. Each of the memory dies includes a memory cell array, an error correction code (ECC) engine and a test circuit. The memory cell array includes a plurality of memory cell rows, each including a plurality of volatile memory cells. The test circuit, in a test mode, generates a test syndrome and an expected decoding status flag indicating error status of the test syndrome, receives test parity data generated by the ECC engine based on the test syndrome and a decoding status flag indicating error status of the test parity data, and determines whether the ECC engine has a defect based on comparison of the test syndrome and the test parity data and a comparison of the expected decoding status flag and the decoding status flag.

Semiconductor memory devices with ECC engine defect determination based on test syndrome, test parity, expected decoding status and received decoding status

Managing memory device with processor-in-memory circuit to perform memory or processing operation

Neural network method and apparatus with floating point processing

A memory device includes a memory bank including a plurality of banks, each including a memory cell array; a calculation logic including a plurality of processor-in-memory (PIM) circuits arranged in correspondence to the banks, each of the plurality of PIM circuits performing calculation processing using at least one selected from data provided from a host and information read from a corresponding bank among the banks; and a control logic configured to control a memory operation on the memory bank in response to a command and/or an address, each received from the host, or to control the calculation logic to perform the calculation processing, wherein reading operations are respectively performed in parallel on the banks for the calculation processing, offsets having different values are respectively configured for the banks, and information is read from different positions in respective memory cell arrays of the banks and provided to the PIM circuits.

Memory device performing parallel calculation processing, operating method thereof, and operating method of memory controller controlling the memory device

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Seoul, South Korea

Sukhan Lee