Apple Inc.

Google Inc.

Sukalpa Biswas

Hao Chen

Shinye Shiu

Manu Gulati

Farid Nemati

Gregory S Mathews

Kai Lun Hsiung

Lakshmi Narasimha Murthy Nukala

Shane J Keil

Sridhar Subramanian

Rakesh L Notani

Yanzhe Liu

Rong Zhang Hu

Brian P Lilly

Gurjeet S Saund

James B Keller

James Han Wang

Harshavardhan Kaushikkar

Robert E Jeter

Thejasvi Magudilu Vijayaraj

Brijesh Tripathi

Gurushankar Rajamani

Jeffrey R Wilcox

Fabien S Faure

Venkata Ramana Malladi

Neeraj Parik

Wolfgang H Klingauf

Benjamin Steel Gelb

Thejasvi Magudilu Vijavaraj

Amin Farmahini

Luka Bodrozic

Vincent R Von Kaenel

Erik P Machnicki

Cyril De La Cropte De Chanterac

Ruchi Wadhawan

Prashant Jain

Priya Ananthanarayanan

Kiran Kattel

Bikram Saha

Peter Fu

Pulkit Desai

Shiva Kumar

Chaitanya Polapragada

Allen Kim

Robert Gries

Timothy John Millet

Peter F Holland

Gerard Richard Williams

Wei-Han Lien

Bin Ni

Marc A Schaub

Shun Wai Go

Munetoshi Fukami

David S Warren

Liang Deng

Enming Zheng

Kai Lun Charles Hsiung

Thejasvi Magudilu Vijayarai

Robert Hu

James Wang

In an embodiment, a memory system may include at least two types of DRAM, which differ in at least one characteristic. For example, one DRAM type may be a high density DRAM, while another DRAM type may have lower density but may also have lower latency and higher bandwidth than the first DRAM type. DRAM of the first type may be on one or more first integrated circuits and DRAM of the second type may be on one or more second integrated circuits. In an embodiment, the first and second integrated circuits may be coupled together in a stack. The second integrated circuit may include a physical layer circuit to couple to other circuitry (e.g., an integrated circuit having a memory controller, such as a system on a chip (SOC)), and the physical layer circuit may be shared by the DRAM in the first integrated circuits.

Memory system having combined high density, low bandwidth and low density, high bandwidth memories

Methods, systems, and apparatus, including computer programs encoded on computer storage media, for processing data on a memory controller. One of the methods comprises obtaining a first request and a second request to access respective data corresponding to the first and second requests at a first memory device of the plurality of memory devices; and initiating interleaved processing of the respective data; receiving an indication to stop processing requests to access data at the first memory device and to initiate processing requests to access data at a second memory device, determining that the respective data corresponding to the first and second requests have not yet been fully processed at the time of receiving the indication, and in response, storing, in memory accessible to the memory controller, data corresponding to the requests which have not yet been fully processed.

Data processing on memory controller

In an embodiment, a memory system may include at least two types of DRAM, which differ in at least one characteristic. For example, one DRAM type may be a high density DRAM, while another DRAM type may have lower density but may also have lower latency and higher bandwidth than the first DRAM type. DRAM of the first type may be on one or more first integrated circuits and DRAM of the second type may be on one or more second integrated circuits. In an embodiment, the first and second integrated circuits may be coupled together in a stack. The second integrated circuit may include a physical layer circuit to couple to other circuitry (e.g. an integrated circuit having a memory controller, such as a system on a chip (SOC)), and the physical layer circuit may be shared by the DRAM in the first integrated circuits.

An apparatus includes a memory circuit and a memory controller circuit. The memory controller circuit may include a write request queue. The memory controller circuit may be configured to receive a memory request to access the memory circuit and determine if the memory request includes a read request or a write request. A received read request may be scheduled for execution, while a received write request may be stored in the write request queue. The memory controller circuit may reorder scheduled memory requests based on achieving a specified memory access efficiency and based on a number of write requests stored in the write request queue.

Ordering memory requests based on access efficiency

Techniques relating to arbitration in a memory controller are disclosed. In some embodiments, the memory controller is configured to transition between read turns and writes turn according to a turn schedule. In some embodiments, the memory controller also receives reports from circuitry requesting memory transactions and determines a current latency tolerance value based on the reports. In some embodiments, the memory controller is configured to switch from a write turn to a read turn prior to a scheduled switch based on the current latency tolerance meeting a threshold value.

Write/read turn techniques based on latency tolerance

An embodiment of an apparatus includes a plurality of processing circuits, a plurality of memory circuits, and a memory controller circuit coupled to each memory circuit via a respective communication channel. A particular processing circuit may generate a data stream that includes a plurality of data blocks. The memory controller circuit may receive the plurality of data blocks from the particular processing circuit. The memory controller circuit may distribute the plurality of data blocks among the plurality of memory circuits based on respective utilizations of the plurality of communication channels.

Memory data distribution based on communication channel utilization

In one embodiment, a system includes a memory that includes a live section and a spares section. The live section may be mapped to the address space of the system, and may be accessed in response to memory operations. Once an entry in the live section has been detected as failed, an entry in the spares section may be allocated to replace the failed entry. During subsequent accesses to the failed entry, the allocated entry may be used instead. In an embodiment, the failed entry may be coded with an indication of the allocated entry, to redirect to the allocated entry. In one implementation, for example, the failed entry may be coded with N copies of a pointer to the allocated entry, each copy protected by corresponding ECC.

Storing address of spare in failed memory location

A memory controller circuit coupled to a memory circuit that includes multiple banks may receive multiple access requests including a particular access request to a particular bank of the plurality of banks. The particular access request is associated with a particular virtual channel of a plurality of virtual channels. The memory controller circuit may select a given access requests of the multiple access requests based on an arbitration category value associated with a virtual channel of the given access request and modify the arbitration category value in response to selecting the given access request.

Memory access scheduling using category arbitration

A method and apparatus for optimizing calibrations of a memory subsystem is disclosed. A memory controller of a memory subsystem includes a memory interface suitable for coupling to a DRAM having a plurality of banks. The memory controller includes a state machine the state machine may initiate calibration of circuitry within the memory controller. Responsive to initiating the calibration, the state machine also causes a refresh command to be transmitted to the DRAM. The calibration is then performed concurrent with the refresh of the DRAM. Subsequent to transmitting the refresh command, the state machine causes the memory interface to be placed into a low power state.

Method and apparatus for optimizing calibrations of a memory subsystem

A memory controller circuit coupled to multiple memory circuits may receive requests to access particular locations within the multiple memory circuits. A request may be assigned a particular quality-of-service level. During operation, the memory controller circuit may reallocate the quality-of-service level of a particular request to a new quality-of-service level based on accumulated bandwidth credits associated with the new quality-of-service level.

Memory access quality-of-service reallocation

A memory controller circuit coupled to multiple memory circuits may receive a read request for a particular one of the memory circuits and insert the read request into one of multiple linked lists that includes a linked list whose entries correspond to previously received read requests and are linked according to respective ages of the read requests. The memory controller circuit may schedule the read request using a head pointer of one of the multiple linked lists.

Memory access scheduling using a linked list

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Fremont, CA, United States of America

Sukalpa Biswas