Samsung Electronics Co., Ltd.

Suk-Pil Kim

Yoon-Dong Park

June-mo Koo

Won-Joo Kim

Won-joo Kim

Jae-woong Hyun

I-hun Song

Young-Gu Jin

Tae-eung Yoon

Tae-Hee Lee

Seung-hoon Lee

Seung-Hwan Song

Young-Soo Park

Hoon Bae Kim

Choong-Ho Lee

Jung-Hoon Lee

Sung-Jae Byun

Seung-Hyuk Chang

Dong-Gun Park

Kwang-Soo Seol

Jong-jin Lee

Tae-Yong Kim

Jung-Chak Ahn

Takashi Noguchi

Kyung-bae Park

Eun-hong Lee

Deok-kee Kim

Hans S Cho

Chang-rok Moon

Sang-Jun Choi

Eun-Suk Cho

Dae-lok Bae

Byung-Yong Choi

Suk-Kang Sung

Kyoung-Iae Cho

Chris Hong

Do-Young Kim

Ho Young Lee

Nae-in Lee

Young-soo Park

Jai-kwang Shin

Jung-hyun Lee

Myoung-jae Lee

Wenxu Xianyu

Ki-ha Hong

Hwa-Sung Rhee

Seung-eon Ahn

Huaxiang Yin

Tae-hun Kim

Kyu-Charn Park

Byoung-Jae Bae

Jang-yeon Kwon

Ji-sim Jung

Chang-Wook Moon

Hoon-sang Oh

Young-gu Jin

Sang-min Shin

Jung-hun Sung

Hyuck Lim

Xiaoxin Zhang

Young-Joon Ahn

Hyuk-soon Choi

Joong S Jeon

Hyuk Soo Lim

Se-Young Cho

Yeon-Sik Park

Hoon-Sang Oh

A field effect transistor having at least one Ge nanorod and a method of manufacturing the field effect transistor are provided. The field effect transistor may include a gate insulation layer formed on a silicon substrate, at least one nanorod embedded in the gate insulation layer having both ends thereof exposed, a source electrode and a drain electrode connected to opposite sides of the at least one Ge nanorod, and a gate electrode formed on the gate insulation layer between the source electrode and the drain electrode.

Field effect transistor having germanium nanorod and method of manufacturing the same

A multi-layered non-volatile memory device and a method of manufacturing the same. The non-volatile memory device may include a plurality of first semiconductor layers having a stack structure. A plurality of control gate electrodes may extend across the first semiconductor layers. A first body contact layer may extend across the first semiconductor layers. A plurality of charge storage layers may be interposed between the control gate electrodes and the first semiconductor layers.

Non-volatile memory device and method of manufacturing the same

An image sensor includes a first substrate including a driving element, a first insulation layer on the first substrate and on the driving element, a second substrate including a photoelectric conversion element, and a second insulation layer on the second substrate and on the photoelectric conversion element. A surface of the second insulation layer is on an upper surface of the first insulation layer. The image sensor includes a conductive connector penetrating the second insulation layer and a portion of the first insulation layer. Methods of forming image sensors are also disclosed.

Image sensors

Image sensors and methods of manufacturing image sensors

Provided are a non-volatile memory device, which may have a stacked structure and may be easily integrated at increased density, and a method of fabricating and using the non-volatile memory device. The non-volatile memory device may include at least one pair of first electrode lines. At least one second electrode line may be between the at least one pair of first electrode lines. At least one data storage layer may be between the at least one pair of first electrode lines and the at least one second electrode line and may locally store a resistance change.

Non-volatile memory devices having data storage layer

Memory devices and methods of manufacturing the same are provided. In a memory device, a memory-switch structure is formed between a first and second electrode. The memory-switch structure includes a memory resistor and a switch structure. The switch structure controls current supplied to the memory resistor. A memory region of the memory resistor and a switch region of the switch structure are different from each other.

Memory devices and methods of manufacturing the same

Provided are a non-volatile memory device which can be extended in a stack structure and thus can be highly integrated, and a method of manufacturing the non-volatile memory device. The non-volatile memory device includes: at least one first electrode, at least one second electrode crossing the at least one first electrode, at least one data storing layer interposed between the at least one first electrode and the second electrode, at a region in which the at least one first electrode crosses the at least one second electrode and at least one metal silicide layer interposed between the at least one first electrode and the at least one second electrode, at the region in which the at least one first electrode crosses the at least one second electrode.

Non-volatile memory device

Provided is a non-volatile memory device having a stacked structure that is easily highly integrated and a method of economically fabricating the non-volatile memory device. The non-volatile memory device may include at least one first electrode and at least one second electrode that cross each other. At least one data storage layer may be disposed on a section where the at least one first electrode and the at least one second electrode cross each other. The at least one first electrode may include a first conductive layer and a first semiconductor layer.

Antifuse structures, antifuse arrays, methods of manufacturing, and methods of operating the same are provided. An antifuse structure includes bitlines formed as first diffusing regions within a semiconductor substrate, an insulation layer formed on the bitlines, and wordlines formed on the insulation layer. An antifuse array includes a plurality of antifuse structures arranged in an array.

Antifuse structures, antifuse array structures, methods of manufacturing the same

Example embodiments provide a capacitorless dynamic random access memory (DRAM), and methods of manufacturing and operating the same. The capacitorless DRAM according to example embodiments may include a semiconductor layer separated from a top surface of a substrate and that contains a source region, a drain region, and a channel region, a charge reserving layer formed on the channel region, and a gate formed on the substrate to contact the channel region and the charge reserving layer.

Capacitorless DRAM and methods of manufacturing and operating the same

Example embodiments provide a non-volatile memory device with increased integration and methods of operating and fabricating the same. A non-volatile memory device may include a plurality of first storage node films and a plurality of first control gate electrodes on a semiconductor substrate. A plurality of second storage node films and a plurality of second control gate electrodes may be recessed into the semiconductor substrate between two adjacent first control gate electrodes and below the bottom of the plurality of first control gate electrodes. A plurality of bit line regions may be on the semiconductor substrate and each may extend across the plurality of first control gate electrodes and the plurality of second control gate electrodes.

Non-volatile memory device and methods of operating and fabricating the same

A nonvolatile memory device includes a plurality of first control gate electrodes, second control gate electrodes, first storage node films, and second storage node films. The first control gate electrodes are recessed into a semiconductor substrate. Each second control gate electrode is disposed between two adjacent first control gate electrodes. The second control gate electrodes are disposed on the semiconductor substrate over the first control gate electrodes. The first storage node films are disposed between the semiconductor substrate and the first control gate electrodes. The second storage node films are disposed between the semiconductor substrate and the second control gate electrodes. A method of fabricating the nonvolatile memory device includes forming the first storage node films, forming the first control gate electrodes, forming the second storage node films, and forming the second control gate electrodes.

Nonvolatile memory devices and methods of fabricating the same

A non-volatile memory device having a stack structure, and a method of operating the non-volatile memory device In which the non-volatile memory device includes a plurality of variable resistors arranged in at least one layer. At least one layer selection bit line and a plurality of bit lines coupled to the plurality of the variable resistors are provided. A plurality of selection transistors coupled between the plurality of the bit lines and the plurality of the variable resistors are provided.

Non-volatile memory device and method of operating the same

Growing community of inventors

Yongin-si, South Korea

Suk-Pil Kim