Skhynix Inc.

Korea Advanced Institute of Science and Technology

Suk Kwang Park

Gil Bok Choi

Min Sang Park

Sung Hoon Cho

Yun Bong Lee

Dong Wook Lee

Jaekyun Moon

Hwang Huh

Myung Su Kim

Soon Ok Seo

Sang Jo Lee

Yeon Joo Jeong

Minsu Choi

Chang Jin Sunwoo

A memory system includes a memory device including a plurality of memory cells, and a controller configured to access the plurality of memory cells. The controller includes a data read block configured to read first data from one or more pages included in first memory cells, determine a target memory cell subject to a compensation based on the first data, and read second data from one or more pages of second memory cells adjacent to the target memory cell, and an equalizer configured to convert the second data into symbol interfering data, check a probability of the first data from a lookup table according to the symbol interfering data, and determine the compensation on the first data based on the probability.

Memory system for interference compensation and operating method thereof

A memory system includes a semiconductor memory device including memory cells and an internal Random Access Memory (RAM); and a controller suitable for transmitting read retry table information to the semiconductor memory device when a read operation for the memory cells fails, wherein the internal RAM stores a read retry table during operation of the memory system, and wherein the semiconductor memory device performs a read retry operation with a read retry voltage determined based on the read retry table and the read retry table information.

Memory system for performing read retry operation and operating method thereof

The present disclosure memory includes a controller for a semiconductor memory device, the device including a memory cell array including a plurality of pages. The controller includes a memory control module suitable for translating a logical address for data provided from a host to a physical address representing one of the plurality of pages, and determining one of a plurality of operation modes based on the physical address and pre-stored parity-related information. The controller further includes and an error correction code circuit suitable for generating parity-data for the data provided from the host according to the determined operation mode.

Memory device with different parity regions

A semiconductor device includes a plurality of memory blocks each including a plurality of memory cells, a circuit group performing a program operation, a read operation and an erase operation on a selected memory block, among the plurality of memory blocks, and a control circuit controlling the circuit group to program the memory cells of the selected memory block in a healing pattern. The healing pattern is programmed before a subsequent program operation is performed on the selected memory block. The memory cells of the healing pattern include erased memory cells and programmed memory cells arranged alternately.

Semiconductor device and method for programming healing patterns on memory blocks

A method of operating a semiconductor memory device includes performing a first program operation to simultaneously increase threshold voltages of memory cells having different target levels to sub-levels lower than the different target levels, verifying the memory cells by using different verify voltages, respectively, performing a second program operation to divide the threshold voltages of the memory cells, and performing a third program operation to increase the threshold voltages of the memory cells to the different target levels, respectively.

Semiconductor memory device and operating method thereof

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Chungcheongbuk-do, South Korea

Suk Kwang Park