Hyundai Electronics Industries Co. Ltd.

Hynix Semiconductor Inc.

Suk Joong Lee

Gyu Tae Hwang

Han Heung Kim

Oh Bong Kwon

Woodward Yang

Jin Kook Choi

Sang Y Kim

An image sensor according to the present invention can detect and correct an error value of a defective pixel. The image sensor includes an error detection circuit for detecting an error by comparing difference between a current pixel value and a previous pixel value with a predetermined reference value and an error correction circuit for correcting an error value from a pixel, by substituting the previous pixel value for the current pixel value.

Method and apparatus for error detection and correction in image sensor

The present invention relates to a picture display using CMOS (Complementary Metal Oxide Semiconductor) image sensor; and, more particularly, to a CMOS image sensor having a testing circuit embedded therein and a method for verifying operation of the CMOS image sensor using the testing circuit. The CMOS image sensor according to the present invention includes a control/interface unit for controlling its operation sensor using a state machine and for interfacing the CMOS image sensor with an external system; a pixel array including a plurality of pixels sensing images from an object and generating analogue signals according to an amount of incident light; a converter for converting the analogue signals into digital signals to be processed in a digital logic circuit; and a testing circuit for verifying operations of the converter and the control/interface unit, by controlling the converter.

CMOS image sensor with testing circuit for verifying operation thereof

Method and apparatus for image data compression that greatly reduces implementational complexity and cost, and improves error correction. These improvements are achieved at various implementational blocks which include a color extraction unit that can perform a first level of compression by reducing the frame size by, e.g., &frac14; or {fraction (1/16)}. This is followed by compression through division by a programmable loss value where the division propagates the remainder to improve image quality. Differential coded modulation is then performed on the extracted color values to further reduce image data size. The result is variable length encoded using preferably a 1's complement approach that further reduces implementational complexity by eliminating VL coding tables. Finally, the VL encoded compressed data is packetized for transmission over a serial bus where the packetization improves error correction.

Apparatus and method for compressing image data received from image sensor having bayer pattern

A microprocessor of a superscalar structure having a datapath, a data cache, a bus unit and first and second pipelines includes a write buffer equipped in the bus unit and a write back buffer in the data cache to reduce write cycles. The write buffer receives data of a burst write cycle from the write back buffer and data of a single write cycle from the datapath. The write buffer in the microprocessor allows data to be written in the write buffer and then to be written in the external memory when the microprocessor is available for performing an external cycle. The processor includes a state machine to control the write buffer and also includes one write buffer for each of the first and second pipelines in order to diminish the write cycles. The write buffers also include a bit block which indicates whether information in the write buffer is written by a cache miss or a hit in a line having a shared state. The state machine includes idle, request, service, backoff (BOFF) and update states in controlling write cycle progression in a pipeline.

Superscalar processor employing a high performance write back buffer controlled by a state machine to reduce write cycles

A bus interface unit has an arbitrating unit, in response to cycle requests received from internal devices of a processor and a resumption request, for determining an internal device having the highest priority and generating a cycle acknowledgment signal representing thereof; a queue input multiplexing unit, in response to the cycle acknowledgment signal, for selecting cycle queue data from the determined internal device to generate selected cycle queue data; a cycle queue storing unit for storing the selected cycle queue data and state information under; and a queue controlling unit for controlling the cycle queue storing unit to store the selected cycle queue data and the state information under the condition that a back-off condition occurs, and for resuming a cycle under the condition that the back-off condition is cleared by using the stored selected cycle queue data based on the state information to provide the resumption request to the arbitrating unit.

Bus interface unit for preventing deadlock

A bus interface unit of a microprocessor which can simultaneously process bus cycle's requests coming from various pipelines during for one cycle in the pipelined high-performance microprocessor of a superscalar type. The bus interface unit includes a bus cycle arbiter for arbitrating a plurality of cycle requests inputted from a plurality of units, a cycle multiplexer for selecting cycle information inputted from the units in response to an arbitration determination of the bus cycle arbiter, a cycle queue for storing selected information, a cycle generator for generating a bus cycle in response to the information stored in the cycle queue, a bus controller for controlling the bus interface unit as a whole, and a write buffer for enabling a next operation without waiting for the core unit to complete its write operation to improve a performance of a memory write cycle. According to the bus interface unit, the bus cycle requests from respective pipelines of the microprocessor are simultaneously processed during one cycle.

Bus interface unit capable of simultaneously proceeding with two bus

An arbitration apparatus using a least recently used (LRU) algorithm, wherein when a plurality of request devices simultaneously request to use a shared resource, such requests are arbitrated in such a manner that the right to use the shared resource is assigned to the request device with the highest priority. The apparatus includes a priority determining unit for receiving shared-resource request signals from a plurality of request devices and resource using order signals respectively associated with the request devices, thereby outputting a grant signal for the request device with the highest priority along with an arbitration-done signal, a recording register for receiving the grant signal, associated with the use of the shared resource, from the priority determining unit, the recording register storing the resource using order based on the grant signal and outputting the stored data to the priority determining unit, and a status machine for receiving the arbitration-done signal from the priority determining unit along with the request signals from the request devices and other control signals, thereby outputting a status information and control signal to the priority determining unit and a recording register control signal to the recording register.

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Ichon-shi, South Korea

Suk Joong Lee