Samsung Electronics Co., Ltd.

Other

Imec

Suk Jin Kim

Hee Seok Kim

Jeongwook Kim

Kyoung June Min

Jeong Wook Kim

Yeon Gon Cho

Hong-Seok Kim

Jong Myon Kim

Sang Suk Lee

Jun Jin Kong

Seung Won Lee

Shi Hwa Lee

Soojung Ryu

Seok Yoon Jung

Min Young Son

Dong-hoon Yoo

Sang Oak Woo

Young Sam Shin

Dong Soo Kang

Soo Jung Ryu

Dong Kwan Suh

Junhee Kim

Dae Young Kim

Osman Allam

Bingfeng Mei

Kyoung Jun Min

Myon Jong Kim

Provided is a method and apparatus for measuring a performance or a progress state of an application program to perform data processing and execute particular functions in a computing environment using a micro architecture. A thread progress tracking apparatus may include a selector to select at least one thread constituting an application program; a determination unit to determine, based on a predetermined criterion, whether an instruction execution scheme corresponds to a deterministic execution scheme having a regular cycle or a nondeterministic execution scheme having an irregular delay cycle with respect to each of at least one instruction constituting a corresponding thread; and a deterministic progress counter to generate a deterministic progress index with respect to an instruction that is executed by the deterministic execution scheme, excluding an instruction that is executed by the nondeterministic execution scheme.

Apparatus and method for thread progress tracking using deterministic progress index

A hardware memory architecture or arrangement suited for multi-processor systems or arrays is disclosed. In one aspect, the memory arrangement includes at least one memory queue between a functional unit (e.g., computation unit) and at least one memory device, which the functional unit accesses (for write and/or read access).

Memory arrangement for multi-processor systems including a memory queue

A processor and a computing system include a processor core and a buffer memory to read word data from a memory. The read word data includes first byte data read by the processor core from the memory. The buffer memory also stores the read word data, and determines whether second byte data requested by the processor core is stored in the buffer memory.

Processor and computer system with buffer memory

Provided is a processor and method of performing speculative load instructions of the processor in which a load instruction is performed only in the case where the load instruction substantially accesses a memory. A load instruction for canceling operations is performed in other cases except the above case, so that problems occurring by accessing an input/output (I/O) mapped memory area and the like at the time of performing speculative load instructions can be prevented using only a software-like method, thereby improving the performance of a processor.

Processor and method of performing speculative load operations of the processor

A format conversion apparatus which converts image data of a band interleave format into image data of a band separate format is provided. The apparatus includes a memory which stores image data of a band interleave format; and a converting module which reads the memory by increasing a read address of the memory for each stride, and converts the image data of the band interleave format into image data of a band separate format.

Format conversion apparatus from band interleave format to band separate format

A tile binning method including: dividing a scene for rendering a triangle, into a plurality of tiles; determining identification values of tile nodes of each of the tiles; and identifying a tile including an entirety or a part of the triangle from the tiles, based on the identification value of the tile nodes for each of the tiles.

Method and system for tile binning using half-plane edge function

A method of sharing a coarse grained array and a processor using the method is provided. A processor includes a first processor core including a plurality of first functional units which execute a first instruction set, a second processor core including a plurality of second functional units which execute a second instruction set, and a coarse grained array including a plurality of third functional units which execute a portion of instructions of the first instruction set and/or the second instruction set, instead of the first processor core and/or the second processor core.

Method of sharing coarse grained array and processor using the method

A method and system for an early Z test in a tile-based three-dimensional rendering is provided. In the method and system for an early Z test, a portion which is not displayed to a user is removed prior to performing a rasterization process, and thereby performing the 3D rendering efficiently. The method includes segmenting a scene into tiles for performing a rendering with respect to a triangle; selecting a first tile of the tiles, which has a tile Z value less than a minimum Z value of the triangle; and performing the rendering with respect to the triangle in remaining tiles excluding the selected first tile of the tiles.

Method and system for early Z test in title-based three-dimensional rendering

A reconfigurable processor comprising a configuration memory for storing a configuration bit for at least one loop configuration; a valid information memory for storing bit information indicating whether an operation in a loop is a delay operation; and at least one processing unit for determining whether an operation in a next cycle is the delay operation by referring to the bit information transmitted from the valid information memory, and selectively performing a change and an implementation of a configuration according to the configuration bit from the configuration memory based on the determined results.

Apparatus and method for optimizing loop buffer in reconfigurable processor

A tubular lever lock includes a protruded connection part formed at the cross section of a pawl which slides along an inner spindle and interfaced with the operation of an eccentric hole of an operation globe. The spindles are structured to form and to protrude with a square pole passing through a latch by an appropriate distance. A key holder is formed on an outer bundle and is connected with a lock cylinder of an outer spindle, which enables a catch hub installed inwardly and elastically to rotate. With regard to the inner bundle and outer bundle, when built in, the key holder of the outer bundle causes connection with the operation globe through a square hole of a catch hub as well as a hole of the square pole.

Tubular lever lock

Growing community of inventors

Seoul, South Korea

Suk Jin Kim