Samsung Electronics Co., Ltd.

Yonsei University

Seoul National University

Kwangwoon University Industry-academic Collaboration Foundation

Samsung Eleotronicc Co., Ltd

Suk-jin Kim

Dong-kwan Suh

Young-hwan Park

Do-Hyung Kim

Dae-Hyun Kim

Kyoung-Hoon Kim

Hyun-Jung Kim

Hyun-jung Kim

Dae-hyun Kim

Ki-seok Kwon

Jae-un Park

Hyeong-Seok Yu

Han-su Cho

Seung-won Lee

Kyoung-hoon Kim

Tai-song Jin

Hong-Seok Kim

Soo-jung Ryu

Jeong-Wook Kim

Dong-Kwan Suh

Si-hwa Lee

Kang-jin Yoon

Young-chul Cho

Chae-Seok Im

Chul-soo Park

Keshava Prasad Nagaraja

Yong-Surk Lee

Jin-sae Jung

Bernhard Egger

Do-hyung Kim

Scott Mahlke

Han-Gu Kim

Kyung-hoon Kim

Won-Jong Lee

Sang-Su Park

Chan-min Park

Min-Wook Ahn

Yong-Jun Park

Dong-wook Kwon

Jae-Hyok Ko

Kwon-taek Kwon

Jun-jin Kong

Seok-hwan Jo

Chae-seok Im

Young-Hwan Park

Jung-uk Cho

Hyunseok Lee

Kyoung-june Min

Hee-seok Kim

Keshava Prasad

Hae-Woo Park

Sang-Bok Han

San Hae Kim

Kyoung-Sik Im

Il-Hun Son

Yeon-bok Lee

Ho-chan Lee

Yonggeun Hong

Han-Su Cho

Jung-Uk Cho

An electronic apparatus for performing machine learning a method of machine learning, and a non-transitory computer-readable recording medium are provided. The electronic apparatus includes an operation module configured to include a plurality of processing elements arranged in a predetermined pattern and share data between the plurality of processing elements which are adjacent to each other to perform an operation; and a processor configured to control the operation module to perform a convolution operation by applying a filter to input data, wherein the processor controls the operation module to perform the convolution operation by inputting each of a plurality of elements configuring a two-dimensional filter to the plurality of processing elements in a predetermined order and sequentially applying the plurality of elements to the input data.

Electronic apparatus for operating machine learning and method for operating machine learning

Provided are a method and apparatus for processing a convolution operation in a neural network. The apparatus may include a memory, and a processor configured to read, from the memory, one of divided blocks of input data stored in a memory; generate an output block by performing the convolution operation on the one of the divided blocks with a kernel; generate a feature map by using the output block, and write the feature map to the memory.

Device and method for processing convolution operation using kernel

Disclosed is an electronic device. The An electronic device including a storage, and a processor configured to perform convolution processing on target data and kernel data based on stride information that indicates an interval at which the kernel data is applied to the target data stored in the storage, in which the processor is further configured to divide the target data into a plurality of pieces of sub-data based on first stride information, perform the convolution processing on the plurality of pieces of sub-data and a plurality of pieces of sub-kernel data respectively corresponding to the plurality of pieces of sub-data based on second stride information that is different from the first stride information, and combine a plurality of processing results, the plurality of pieces of sub-kernel data are obtained by dividing the kernel data based on the first stride information, and the second stride information indicates that the interval at which the kernel data is applied to the target data is 1.

Electronic device and control method thereof

Disclosed is an electronic device and method for controlling same. The electronic device comprises: a memory; and a processor which checks an operation instruction for filtering input data of a neural network for each filter of a main pattern selected from a plurality of filters generated according to learning by the neural network, and stores the checked operation instruction in the memory.

Electronic device and method for controlling same

A processor for performing deep learning is provided herein. The processor includes a processing element unit including a plurality of processing elements arranged in a matrix form including a first row of processing elements and a second row of processing elements. The processing elements are fed with filter data by a first data input unit which is connected to the first row processing elements. A second data input unit feeds target data to the processing elements. A shifter composed of registers feeds instructions to the processing elements. A controller in the processor controls the processing elements, the first data input unit and second data input unit to process the filter data and target data, thus providing sum of products (convolution) functionality.

Processor and control methods thereof for performing deep learning

An operation processing apparatus is provided. The operation processing apparatus includes a vector operator and cores. The vector operator processes a vector operation with respect to an instruction that uses the vector operation, and each core includes a scalar operator that processes a scalar operation with respect to an instruction that does not use the vector operation. The vector operator is shared by the cores.

Vector processing core shared by a plurality of scalar processing cores for scheduling and executing vector instructions

In a method to execute instructions, at least one instruction executed in a predetermined cycle is acquired based on information included in each of a plurality of instructions, and a code included in the at least one instruction acquired. An instruction is allocated to at least one slot based on the analysis result, and a slot necessary to execute the instruction is selectively used. Accordingly, power consumption of a device using the method may be reduced.

Method and processor for implementing an instruction including encoding a stopbit in the instruction to indicate whether the instruction is executable in parallel with a current instruction, and recording medium therefor

Provided is a data processing method including the operations of storing, in a register, a first immediate portion included in a first instruction, from among the first immediate portion and a second immediate portion that constitute an immediate value, which is an operand; determining the immediate value by catenating the second immediate portion included in a second instruction with the stored first immediate portion; and performing an operation by using a value indicated by the second instruction and the determined immediate value.

Method and device for processing an instruction having multi-instruction data including configurably concatenating portions of an immediate operand from two of the instructions

A computing system is disclosed. The computing system according to one embodiment of the present disclosure comprises: a memory device for storing an application program; a processor for executing a loader for loading data of the application program into a memory space allocated for execution of the application program; a local memory having a width corresponding to the size of a register of the processor; and a constant memory having a width smaller than that of the local memory, wherein, according to the size of constant data included in the application program, the processor loads the constant data into one of the local memory and the constant memory.

Computing system, and driving method and compiling method thereof

A VLIW (Very Long Instruction Word) interface device includes a memory configured to store instructions and data, and a processor configured to process the instructions and the data, wherein the processor includes an instruction fetcher configured to output an instruction fetch request to load the instruction from the memory, a decoder configured to decode the instruction loaded on the instruction fetcher, an arithmetic logic unit (ALU) configured to perform an operation function if the decoded instruction is an operation instruction, a memory interface scheduler configured to schedule the instruction fetch request or a data fetch request that is input from the arithmetic logic unit, and a memory operator configured to perform a memory access operation in accordance with the scheduled instruction fetch request or data fetch request.

VLIW interface device and method for controlling the same

Provided are a method and apparatus for processing a very long instruction word (VLIW) instruction. The method includes acquiring a calculation allocation instruction including information regarding whether the VLIW instructions are allocated to a plurality of slots; updating a database including the information regarding whether the VLIW instructions are allocated to the plurality of slots based on the acquired calculation allocation instruction; and allocating at least one VLIW instruction to each of the plurality of slots based on the updated database.

Method and device for allocating a VLIW instruction based on slot information stored in a database by a calculation allocation instruction

A multi-thread processor and a method of controlling a multi-thread processor are provided. The multi-thread processor includes at least one functional unit; a mode register; and a controller configured to control the mode register to store thread mode information corresponding to a task to be processed among a plurality of thread modes, wherein the plurality of thread modes are divided based on a size and a number of at least one thread that is concurrently processed in one of the at least one functional unit, allocate at least one thread included in the task to the at least one functional unit based on the thread mode information stored in the mode register and control the at least one functional unit to process the at least one thread.

Multi-thread processor and controlling method thereof

A memory management method includes determining a stride value for stride access by referring to a size of two-dimensional (2D) data, and allocating neighboring data in a vertical direction of the 2D data to a plurality of banks that are different from one another according to the determined stride value. Thus, the data in the vertical direction may be efficiently accessed by using a memory having a large data width.

Memory management method and apparatus

Disclosed is an apparatus comprising: a plurality of memory banks; and a controller for generating a plurality of lookup tables storing data, needed for vector arithmetic operations, copied from data stored in the plurality of memory banks, and generating vector data by reading the data in the generated lookup tables.

Method and apparatus for performing vector operations using look up tables

Provided are a reconfigurable processor and a method of operating the same, the reconfigurable processor including: a configurable memory configured to receive a task execution instruction from a control processor; and a plurality of reconfigurable arrays, each configured to receive configuration information from the configurable memory, wherein each of the plurality of reconfigurable arrays simultaneously executes a task based on the configuration information.

Reconfigurable processor and operation method therefor

Growing community of inventors

Seoul, South Korea

Suk-jin Kim