Skhynix Inc.

Hydis Technologies Co., Ltd.

Korea Advanced Institute of Science and Technology

Samsung Display Co., Ltd.

Suk Hwan Choi

Gyu Hyeong Cho

Chan Hui Jeong

Hyang Yul Kim

Dong Hun Kwak

Chan Keun Kwon

Jong Seok Jung

Choon Hyop Lee

Nak Cho Choi

Soon Ju Jang

Dae Suk Kim

In Nam Lee

Su Wan Woo

Tae Hyun Jun

Seung Geun Baek

Young Kuil Joo

Yoon Seok Choi

Heung Seok Go

Young Kwan Lee

Seung Jun Baek

Choel Hwan Lee

Byung Hoon Kim

Cheol Hwan Lee

Jin Yeop Kim

Sun Beom Lee

Kyeong Hwan Park

A semiconductor device includes a sensing voltage line disposed between a first circuit area and a second circuit area, and configured to transfer a sensing voltage detected in the second circuit area to the first circuit area; and a first internal voltage line disposed between the first circuit area and the second circuit area, configured to transfer an internal voltage, generated by a voltage driver of the first circuit area using the sensing voltage provided through the sensing voltage line, to the second circuit area and configured to shield the sensing voltage line.

Semiconductor device having shielding structure

A storage device includes a memory device and a controller. The memory device includes a memory region configured by a plurality of memory cells. The controller is configured to set at least one prohibited threshold voltage distribution for the memory region based on a result of an operation on the memory region.

Storage device for setting prohibited threshold voltage distribution

A leakage current detection circuit includes: a mirror circuit configured to copy a leakage current flowing through a node and generate a copy current in a copy node; an oscillation circuit including a charge storage unit, the oscillation circuit being connected to the copy node, charged with the copy current, and configured to generate an oscillation signal by charging and discharging the charge storage unit; and a calculation circuit configured to calculate an amount of the leakage current based on the oscillation signal.

Leakage current detection circuit

The present technology includes: a current mirror configured to apply a test current that is generated by a test voltage to a selected word line, among a plurality of word lines, and to generate a copy current by copying the test current; a comparison circuit configured to compare at least one reference current with the copy current to generate a comparison result signal; and a test control circuit configured to perform a first noise control mode that charges unselected word lines, among the plurality of word lines, with electric charges, in response to a test mode signal and floats the unselected word lines.

Test circuit for detecting word line defect and semiconductor apparatus including the same

A power circuit includes a plurality of regulators and a plurality of in-rush current controllers. The plurality of regulators is coupled to an external power voltage and configured to adjust a level of an input voltage to generate a plurality of internal power voltages. The plurality of in-rush current controllers is configured to provide the input voltage to the plurality of regulators, the input voltage corresponding to an increasement voltage. The increasement voltage has a level rising at a preset rate until the plurality of internal power voltages all reach a target level.

Apparatus for controlling in-rush current and an operation method thereof

A semiconductor memory device includes a plurality of memory blocks and a contact region. Each of the plurality of memory blocks includes a plurality of memory cells. The contact region is formed between the plurality of memory blocks. The semiconductor memory device uses a first memory block that is not adjacent to the contact region and a second memory block adjacent to the contact region among the plurality of memory blocks differently.

Semiconductor memory device and method of operating the semiconductor memory device

A temperature sensor and a method of controlling the temperature sensor are provided. The temperature sensor includes a voltage generator suitable for generating a temperature voltage that has a voltage level determined according to a temperature and a reference voltage that has a constant voltage level independent of a change in temperature, a code generator suitable for generating an initial code based on the temperature voltage and the reference voltage, and a code calibrator suitable for generating a calibrated code based on the initial code and a calibration factor.

Temperature sensor and method for controlling the temperature sensor

Temperature sensor, memory device and method for controlling the temperature sensor

A voltage generation circuit includes an amplifier configured to detect a difference between a reference voltage and a feedback voltage according to a control signal and a bias current, and configured to generate a driving signal. The voltage generation circuit also includes a driver configured to generate an internal voltage by driving an external voltage according to the driving signal. The amount of the bias current may be forcibly adjusted by the control signal.

Amplifier and voltage generation circuit including the same

The digital temperature sensing circuit includes a temperature voltage generator configured to generate a temperature voltage varying with a temperature in response to a first reference voltage, divide a supply voltage in response to a second reference voltage, and generate a high voltage and a low voltage, a code voltage generator configured to divide the second reference voltage based on the high voltage and the low voltage and output divided voltages having different voltage levels, and a mode selector supplied with the temperature voltage and the divided voltages, and configured to output a first code or a second code in response to a mode select signal, wherein the first code and the second code have different numbers of bits.

Digital temperature sensing circuit

A memory apparatus includes an internal circuit configured to output a plurality of output signals, a signal conversion circuit configured to convert a control signal to generate a selection signal, and a selection circuit configured to output one of the plurality of output signals based on the selection signal. The memory apparatus also includes a buffer configured to buffer output of the selection circuit and output the buffered output to a pad.

Memory apparatus having structure coupling pad and circuit

A display device includes a touch screen panel folded based on a folding axis, and at least one touch electrode on the folding axis. Each of the touch electrodes on the folding axis may include a graphene layer, a metal mesh layer, and an adhesion metal mesh layer. The grapheme layer may be along the folding axis on a transparent substrate. The first metal mesh layer may be on the transparent substrate to adhere to a lateral surface of the first graphene layer. The first adhesion metal mesh layer may be on a boundary portion between the first graphene layer and the first metal mesh layer.

Display device and method of manufacturing the same

A driver for semiconductor memory, comprising: a storage unit configured to match and store a memory cell address and bucket charge current data corresponding to the memory cell address; a selection controller configured to receive the memory cell address and a target charge current data, and output a bucket charge current select signal and a target charge current select signal corresponding to the bucket charge current data and the target charge current data, respectively, by referring to the storage unit; and a current supply unit configured to supply a bucket charge current and a target charge current in response to the bucket charge current select signal and the target charge current select signal, respectively.

Driver for a semiconductor memory and method thereof

A driver for a semiconductor memory may reduce an error in writing data in memory cells by adjusting the height and width of a spike current, when the memory cells in which data having the same level are written are arranged at different distances. In addition, the driver may reduce the error by controlling the amount of charges supplied to each of the memory cells that are arranged at different distances.

Growing community of inventors

Gyeonggi-do, South Korea

Suk Hwan Choi