International Business Machines Corporation

Suk Hoon Ku

Bruce Bennett Doris

Edward J Nowak

Brent A Anderson

Dureseti Chidambarrao

Jeffrey W Sleight

John J Ellis-Monaghan

Judson Robert Holt

Amlan Majumdar

Renee Tong Mo

Michael John Hargrove

Zhibin Ren

Ashima B Chakravarti

Patrick Ronald Varekamp

Dinkar Virendra Singh

Scott W Crowder

Woo-Hyeong Lee

Ryan Matthew Mitchell

Jeremy John Kempisty

L Ronald Logan

Brent Alan Anderson

Disclosed are embodiments of an integrated circuit structure with field effect transistors having differing divot features at the isolation region-semiconductor body interfaces so as to provide optimal performance versus stability (i.e., optimal drive current versus leakage current) for logic circuits, analog devices and/or memory devices. Also disclosed are embodiments of a method of forming the integrated circuit structure embodiments. These method embodiments incorporate the use of a cap layer pullback technique on select semiconductor bodies and subsequent wet etch process so as to avoid (or at least minimize) divot formation adjacent to some but not all semiconductor bodies.

Differential nitride pullback to create differential NFET to PFET divots for improved performance versus leakage

A semiconductor fabrication method. The method includes providing a semiconductor substrate, wherein the semiconductor substrate includes a semiconductor material. Next, a top portion of the semiconductor substrate is removed. Next, a first semiconductor layer is epitaxially grown on the semiconductor substrate, wherein a first atomic percent of a first semiconductor material in the first semiconductor layer is equal to a substrate atomic percent of the substrate semiconductor material in the semiconductor substrate.

Method for improving semiconductor surfaces

A semiconductor device structure includes at least two field effect transistors formed on same substrate, the first field effect transistor includes a spacer having a first width, the second field effect transistor includes a compressive spacer having a second width, the first width being different than said second width. Preferably, the first width is narrower than the second width. A tensile stress dielectric film forms a barrier etch stop layer over the transistors.

High performance CMOS device structures and method of manufacture

A non-critical block mask exposes one of the source and drain in an SOI FET, which is implanted with a leakage implant that increases the leakage in the exposed element, thus providing a conductive path to draw away holes from the transistor body.

Compact body for silicon-on-insulator transistors requiring no additional layout area

A method of forming a self-aligned vertical double-gate metal oxide semiconductor field effect transistor (MOSFET) device is provided that includes processing steps that are CMOS compatible. The method include the steps of growing an oxide layer on a surface of a silicon-on-insulator (SOI) substrate, said SOI substrate having a buried oxide region located between a top Si-containing layer and a bottom Si-containing layer, wherein said top and bottom Si-containing layers are of the same conductivity-type; patterning and etching gate openings in said oxide layer, said top Si-containing layer and said buried oxide region stopping on said bottom Si-containing layer of said SOI substrate; forming a gate dielectric on exposed vertical sidewalls of said gate openings and filling said gate openings with silicon; removing oxide on horizontal surfaces which interface with said Si-containing bottom layer; recrystallizing silicon interfaced to said gate dielectric and filling said gate openings with expitaxial silicon; forming a mask on said oxide layer so as cover one of the silicon filled gate openings, while leaving an adjacent silicon filled gate opening exposed; selectively implanting dopants of said first conductivity-type into said exposed silicon filled gate opening and activating the same, wherein said dopants are implanted at an ion dosage of about 1E15 cm or greater; selectively etching the exposed oxide layer and the underlying top Si-containing layer of said SOI substrate stopping on said buried oxide layer; removing said mask and implanting a graded-channel dopant profile in said previously covered silicon filled gate opening; etching any remaining oxide layer and forming spacers about said silicon filled gate openings; and saliciding any exposed silicon surfaces.

Method for self-aligned vertical double-gate MOSFET

Growing community of inventors

Beacon, NY, United States of America

Suk Hoon Ku