Samsung Electronics Co., Ltd.

Suk-Ho Joo

Hideki Horii

Ji-Hye Yi

Kyung-rae Byun

Ki-hong Lee

Choong-ryul Paik

Kyung-Chang Ryoo

Byeong-Ok Cho

Gyung-Jin Min

Jong Chae Moon

Yoo-Chul Kong

Seong-Soo Lee

Hee-Seok Kim

Dae-Hyun Jang

Min-Joon Park

Hyoung-seub Rhie

Hwa-Young Ko

Han-Geun Yu

Jin-Hwan Ham

A method of manufacturing a semiconductor device comprises forming memory cells on a memory cell region, alternately forming a sacrificial layer and an insulating interlayer on a connection region for providing wirings configured to electrically connect the memory cells, forming an etching mask pattern including etching mask pattern elements on a top sacrificial layer, forming blocking sidewalls on either sidewalls of each of the etching mask pattern element, forming a first photoresist pattern selectively exposing a first blocking sidewall furthermost from the memory cell region and covering the other blocking sidewalls, etching the exposed top sacrificial layer and an insulating interlayer to expose a second sacrificial layer, forming a second photoresist pattern by laterally removing the first photoresist pattern to the extent that a second blocking sidewall is exposed, and etching the exposed top and second sacrificial layers and the insulating interlayers to form a staircase shaped side edge portion.

Methods of manufacturing a semiconductor device and a semiconductor memory device thereby

Provided is a method of forming a contact structure. The method includes forming a conductive pattern on a substrate. An interlayer insulating layer covering the conductive pattern is formed. The interlayer insulating layer is patterned to form an opening partially exposing the conductive pattern. An oxide layer is formed on substantially the entire surface of the substrate on which the opening is formed. A reduction process is performed to reduce the oxide layer. Here, the oxide layer on a bottom region of the opening is reduced to a catalyst layer, and the oxide layer on a region other than the bottom region of the opening is reduced to a non-catalyst layer. A nano material is grown from the catalyst layer, so that a contact plug is formed in the opening.

Method of forming contact structure

A phase-changeable memory device may include a substrate, an insulating layer on the substrate, first and second electrodes, and a pattern of a phase-changeable material between the first and second electrodes. More particularly, the insulating layer may have a hole therein, and the first electrode may be in the hole in the insulating layer. Moreover, portions of the second electrode may extend beyond an edge of the pattern of phase-changeable material. Related methods are also discussed.

Phase changeable memory device structures

Disclosed are a semiconductor device and a related method of manufacture. The semiconductor device comprises a semiconductor substrate, a conductive structure including contact regions and gate structures formed on the semiconductor substrate, a protection layer formed on the gate structures, an insulation layer formed on the protection layer, and a plurality of contacts directly contacting the contact regions and the semiconductor substrate through the insulation layer, wherein the contacts have substantially different heights from each other.

Semiconductor device and related method of manufacture

In a phase changeable memory device and a method of formation thereof, the phase changeable memory device comprises: a lower electrode pattern on an interlayer insulating layer; an insulating pattern located on the lower electrode pattern; a phase changeable pattern penetrating the insulating pattern and the lower electrode pattern to contact the lower electrode pattern and the interlayer insulating layer; and an upper electrode on the phase changeable pattern.

Phase changeable memory device and method of formation thereof

Phase changable memory device structures

Methods for forming phase changeable memory devices

The present invention discloses a ferroelectric memory device and a method of forming the same. The ferroelectric memory device includes a semiconductor substrate, a capacitor lower electrode, a ferroelectric layer, and a capacitor upper electrode. The semiconductor substrate has a lower structure. The capacitor lower electrode has a cylindrical shape and a certain height. The ferroelectric layer is conformally stacked over substantially the entire surface of the semiconductor substrate including the capacitor lower electrode. The capacitor upper electrode has a spacer shape and is formed around the sidewall of the ferroelectric layer that surrounds the lower electrode. In the method of forming the ferroelectric memory device, a semiconductor substrate having an interlayer dielectric layer and a lower electrode contact formed through the interlayer dielectric layer is prepared. A cylindrical capacitor lower electrode is formed on the interlayer dielectric layer to cover the contact. A ferroelectric layer is conformally stacked at the semiconductor substrate having the capacitor lower electrode. A spacer-shaped upper electrode is formed around the sidewall of the ferroelectric layer that surrounds the capacitor lower electrode.

Ferroelectric memory device and method of forming the same

Ferroelectric memory device

A MOS transistor employing a titanium-carbon-nitride (TiCN) gate electrode is provided. The MOS transistor has a gate insulating film, a gate electrode, and a source/drain region on a semiconductor substrate. The gate electrode is formed of a single TiCN film or a double film having a TiCN film and a low-resistant metal film formed thereon. The TiCN gate electrode exhibits a low resistance of about 80-100 .mu..OMEGA.-cm and can control variations in Fermi energy level.

Mos transistor adopting titanium-carbon-nitride gate electrode and

Methods of producing ferroelectric capacitors where the electrodes are formed in a contact hole. These methods include the steps of forming an insulating layer on an integrated circuit substrate. A contact hole is then formed through the insulating layer layer to expose a region of the integrated circuit substrate and to define a storage node pattern. A layer of oxidation-resistant conductive material is formed in the contact hole and the insulating layer removed to define a first storage electrode by exposing the layer of oxidation-resistant conductive material. A ferroelectric layer is then formed on the first storage electrode and a second storage electrode is formed on the ferroelectric layer opposite the first storage electrode.

Methods of fabricating ferroelectric capacitors

MOS transistor adopting titanium-carbon-nitride gate electrode and

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Seoul, South Korea

Suk-Ho Joo