Korea Institute of Science and Technology

Korea Advanced Institute of Science and Technology

Suk Hee Han

Hyun Woo Koo

Joon Yeon Chang

Hyung Jun Kim

Kyung Ho Kim

Woo Young Lee

Seung Young Park

Joonyeon Chang

Jin Dong Song

Young Keun Kim

Chul Soon Park

Hi Jung Kim

Jun Woo Choi

Hyung-jun Kim

Byoung Chul Min

Kyung Ho Shin

Hye Jung Chang

Min Cheol Shin

Jong Hwa Eom

Woong Hwang

Jin-Dong Song

Jae Wan Shim

Won Young Choi

Moo Whan Shin

Kwan Hyi Lee

Hyun Jung Yi

Joo Hyeon Lee

Sang Hoon Shin

Tae Eon Park

Hee Young Kwon

Kyoung Il Lee

Dal Young Kim

Hyun Cheol Koo

Yun Myung Kim

Han Joo Lee

Jung Mi Lee

Ki Hyeon Kim

Jae Min Myoung

Min Hong Jeun

Jang Hae Ku

Inn Yeal Oh

Cha Un Jang

Provided is a method of a generating a skyrmion. The method includes a step of preparing a magnetic multilayer system and a step of generating a skyrmion at a temperature of 400&#xb0; C. or higher by adjusting the magnetic anisotropy value and the magnetization value of the magnetic multilayer system.

Method and apparatus for generating skyrmion lattice stabilized at high temperature

Provided is a reconfigurable logic device using an electrochemical potential. The device includes first and second semiconductor channels, where an effective magnetic field direction of a channel is controlled by a current direction and which are spaced apart from each other, a first ferromagnetic gate contacting the first semiconductor channel and a second ferromagnetic gate contacting the second semiconductor channel, where a magnetization direction is controlled by a gate voltage, and a control unit configured to calculate a difference value corresponding to a difference between a first determination value and a second determination value, and compare the difference value with a reference value to determine an output value.

Reconfigurable logic device using electrochemical potential

A spin control electronic device operable at room temperature according to an embodiment of the present invention includes a transfer channel that includes a low-dimensional nanostructure, the nanostructure being located on a substrate, having an elongate shape in a first direction and having a cross section, cut along a second direction that is perpendicular to the first direction, in the shape of a triangle; a source electrode located on the substrate and intersecting the transfer channel, the source electrode covering part of the transfer channel; and a drain electrode spaced apart from the source electrode on the substrate, the drain electrode intersecting the transfer channel and covering part of the transfer channel.

Spin control electronic device operable at room temperature

A spin transistor includes: an input part that is made of a material exhibiting a spin Hall effect and configured to transfer electrons with a predetermined direction of spin to a connecting part; and the connecting part that receives the electrons with the predetermined direction of spin from the input part, rotates the spin of the electrons in accordance with a gate voltage applied to the gate electrode, and transfers the electrons to the output part.

Ferromagnet-free spin transistor and method for operating the same

A complementary device including a gate electrode, a channel, a source electrode connected to the gate electrode and the channel, and a first drain electrode and a second drain electrode connected to the gate electrode and the channel is provided. The first/second drain electrode is formed so that, in accordance with a voltage applied to the gate electrode, electron spins injected into the source electrode are moved from the source electrode to the first/second drain electrode through the channel while rotating in a first/second direction. Directions of the electron spins that reach the first drain electrode and the second drain electrode are opposite to each other.

Complementary spin device having a gate, a source, a first and second drain electrode

A method for simulating fluid flow includes: discretizing a space in which a fluid flows into a regular lattice; assuming that fluid particles repetitively move and collide in the lattice; deriving a univariate polynomial equation by comparing the n-th (n is a non-negative integer) order momentum of velocity between the Maxwell-Boltzmann distribution and the discretized Maxwell-Boltzmann distribution; calculating the weight coefficients corresponding to the discrete velocities of the fluid particles based on the univariate polynomial equation; and deriving a lattice Boltzmann model using the weight coefficients. A lattice Boltzmann model with superior stability and accuracy may be derived easily.

Method for simulating fluid flow and recording medium for performing the method

A complementary logic device includes: an insulating layer formed on a substrate; a source electrode formed of a ferromagnetic body on the insulating layer; a gate insulating film; a gate electrode formed on the gate insulating film and controlling a magnetization direction of the source electrode; a channel layer formed on each of a first side surface and a second side surface of the source electrode and transmitting spin-polarized electrons from the source electrode; a first drain electrode formed on the first side surface of the source electrode; and a second drain electrode formed on the second side surface of the source electrode, wherein a magnetization direction of the first drain electrode and a magnetization direction of the second drain electrode are antiparallel to each other. Therefore, not only characteristics of low power and high speed but also characteristics of non-volatility and multiple switching by spin may be obtained.

Complementary logic device using spin injection

Disclosed herein are a method of generating a two-dimensional hole gas (2DHG) using a type-2 quantum well formed using semiconductors with different electron affinities or band gap, and a high-speed p-type semiconductor device using the 2DHG. To this end, the method includes providing a semiconductor substrate; growing a first semiconductor layer on the semiconductor substrate, growing a second semiconductor layer with a different electron affinity or band gap from the first semiconductor layer on the first semiconductor layer, and growing a third semiconductor layer with a different electron affinity or band gap from the second semiconductor layer, thereby forming a type-2 quantum well; and forming a p-type doping layer in the vicinity of the type-2 quantum well, thereby generating the 2DHG.

P-type semiconductor device comprising type-2 quantum well and fabrication method thereof

A logic device includes: a substrate having a channel layer; two input terminal patterns of ferromagnetic material formed on the substrate and spaced apart from each other along a longitudinal direction of the channel layer so as to serve as the input terminals of a logic gate; and an output terminal pattern of ferromagnetic material formed on the substrate and disposed between the two input terminal patterns to serve as an output terminal of the logic gate. The output terminal pattern reads an output voltage by using spin accumulation and diffusion of electron spins which are injected into the channel layer from the input terminal patterns.

Reconfigurable logic device using spin accumulation and diffusion

A spin transistor that includes: a semiconductor substrate including an upper cladding layer and a lower cladding layer, and a channel layer interposed between the upper and lower cladding layers; a ferromagnetic source and a ferromagnetic drain formed on the semiconductor substrate and spaced from each other in a length direction of the channel layer; and a gate electrode formed on the semiconductor substrate between the source and the drain and having applied a gate voltage thereto to control a spin precession of an electron passing through the channel layer, wherein the semiconductor substrate includes a first carrier supply layer of a first conductivity type disposed below the lower cladding layer and supplying carriers to the channel layer, and a second carrier supply layer of a second conductivity type opposite to the first conductivity type formed on the upper cladding layer and supplying the carriers to the channel layer.

Spin transistor using N-type and P-type double carrier supply layer structure

There is provided a complementary spin transistor logic circuit, including: a parallel spin transistor that includes a magnetized first source, a first drain magnetized in parallel with the magnetization direction of the first source, a first channel layer and a first gate electrode; and an anti-parallel spin transistor that includes a magnetized second source, a second drain magnetized in anti-parallel with the magnetization direction of the second source, a second channel layer and a second gate electrode, wherein the first gate electrode and the second gate electrode are connected to a common input terminal.

Complementary spin transistor logic circuit

A spin transistor includes a semiconductor substrate including a channel layer having a 2-dimensional electron gas structure and upper and lower cladding layers disposed respectively in upper and lower sides of the channel layer; ferromagnetic source and drain electrodes formed on the semiconductor substrate and disposed spaced apart from each other; a gate electrode disposed between the source electrode and the drain electrode and having a gate voltage applied thereto in order to control the spin of electrons passed through the channel layer; a first carrier supply layer disposed between the lower cladding layer and the channel layer to supply carriers to the channel layer; and a second carrier supply layer disposed between the upper cladding layer and the channel layer to supply carriers to the channel layer.

Spin transistor using double carrier supply layer structure

A spin transistor conducive to the miniaturization and large scale integration of devices, because a magnetization direction of a source and a drain is determined by a direction of the epitaxial growth of a ferromagnet. The spin transistor includes a semiconductor substrate having a channel layer formed thereinside; ferromagnetic source and drain epitaxially grown on the semiconductor substrate and magnetized in a longitudinal direction of the channel layer due to magnetocrystalline anisotropy&#x2014;the source and drain being disposed spaced apart from each other in a channel direction and magnetized in the same direction&#x2014;; and a gate disposed between the source and the drain to be insulated with the semiconductor substrate and formed on the semiconductor substrate to control the spin of electrons that are passed through the channel layer.

Spin transistor using epitaxial ferromagnet-semiconductor junction

A magnetic memory device includes a substrate for reading and a magnetic memory cell. The substrate has a channel layer. The magnetic memory cell is formed on the substrate and has a magnetized magnetic material that transfers spin data to electrons passing the channel layer. Data stored in the magnetic memory cell are read by a voltage across both side ends of the channel layer that is generated when the electrons passing the channel layer deviate in the widthwise direction of the channel layer by a spin Hall effect.

Magnetic memory device and method for reading magnetic memory cell using spin hall effect

Disclosed herein is a spin transistor including: a semiconductor substrate having a channel layer formed therein; first and second electrodes which are formed to be spaced apart from each other on the substrate at a predetermined distance along a longitudinal direction of the channel layer; a source and drain which include magnetized ferromagnetic materials and are formed to be spaced apart form each other between the first electrode and the second electrode at a predetermined distance along the longitudinal direction of the channel layer; and a gate which is formed on the substrate between the source and the drain, and adjusts spin orientations of electrons passing through the channel layer, wherein the electrons passing through the channel layer are spin-aligned at a lower side of the source by a stray magnetic field of the source and spin-filtered at a lower side of the drain by a stray field of the drain.

Growing community of inventors

Seoul, South Korea

Suk Hee Han