Electronics and Telecommunications Research Institute

Suk-Han Yoon

Seong-Woon Kim

Jong-Seok Han

Woo-Jong Hahn

Won-Sae Sim

Sang-Seok Shin

Chul-Ho Won

Jong-Seok Hahn

Sang-Man Moh

A broadcast transfer method for transferring the same data from any one node of the interconnection network of the parallel processing computer to every other nodes. The object of the present invention is to provide a broadcast transfer method for a hierarchical interconnection network with multiple tags which can be easily expanded, wherein each switch can perform a routing control function, and which enables the same packet to be transferred irrespective of the receiving group of each layer even when multiple tags are used in the same manner as in the point-to-point packet transfer. The broadcast transfer method for a hierarchical interconnection network with multiple tags in accordance with the present invention comprises the steps of using a single tag structure; discriminating if a routing switch belongs to a layer one cluster interconnection network or a layer two cluster interconnection network by using a hub/cluster discrimination signal; and outputting the corresponding packet type in accordance with the input location where a packet is received at the corresponding routing switch to enable all receiving nodes to receive the same data.

Broadcast transfer method for a hierarchical interconnection network with multiple tags

A message-passing multiprocessor system, such as, a network interface, a method for transferring messages between a node and a node, and a method for formatting the same in a message-passing computer system are disclosed herein. In the network interface for a computer system there are a plurality of nodes connected with one another through an interconnection network for communicating messages, and more than one processor, and a local shared memory, which are connected with one another through a node bus. These components are connected via the network interface to the interconnection network, the multiprocessor comprises a local bus acting as a path for transferring data in the network interface, a bus connection for connecting the node bus and the local bus, a transferring component for packetizing the messages requested by the processor, if data message, by reading them out from the local shared memory via the local bus, the bus connection and the node bus to produce a packet, and sending the packet to the interconnection network, and a receiver for receiving the message packet from the interconnection network, restoring it to produce a restored message and, if data portion of the data message, storing the restored packet body into the local shared memory through the local bus, the bus connection and the node bus.

Message-passing multiprocessor system

A non-blocking fault tolerant gamma network for a multi-processor system is disclosed, including: N dual links respectively connected to n source nodes, and for transmitting data input; a first stage made up with n 2.times.3 switching devices for outputting data transmitted from the N dual links; a second stage made up with n 3.times.4 switching devices for outputting data output from the first stage; a third stage to n-1 stage made up with (n-2).times.N 4.times.4 switching devices for receiving data output from the second stage at the third stage and outputting the data to n-1 stage; an n stage made up with n 4.times.2 circuits for receiving data output from the n-1 stage and outputting the data; and n dual links connected to n destination nodes for transmitting data output from the n stage, whereby the links, which connect the n source nodes, switching devices of the interconnection network and n destination nodes, are designed according to the connection formula of the certain regulation, thus simultaneously set all paths between a plurality of sources and a plurality of destinations, and tolerate a single-switching fault or a single-link fault in the interconnection network.

Non-blocking fault-tolerant gamma network for multi-processor system

A memory data path controller for a large-scale parallel processing computer system in which, when a network interface and bus interface request access to a single-port memory, a dual path controller dividedly stores memory access requests in network queue and bus queue. This allows a single-port DRAM to be used as a dual-port memory device. Further, the network queue and bus queue are multi-staged to store sequential memory requests and transmit reading/writing data of the network queue or bus queue to the DRAM memory.

Growing community of inventors

Daejeon, South Korea

Suk-Han Yoon