Electronics and Telecommunications Research Institute

Suk Han Yoon

Woo Jong Hahn

Sang Man Moh

Jong Seok Han

Chee Hang Park

Joong Bae Kim

Kee Wook Rim

Gil Rok Oh

Jong Seok Hahn

Yong Yeon Kim

Sang Seok Shin

Won Sae Sim

Jae Kyung Lee

Hae Jin Kim

An Do Ki

Kyong Park

Jin Pyo Kim

The present invention relates to a node connection apparatus. The 3-link node interconnection apparatus and parallel processing apparatus using the same confirm expanding nodes freely, only using fixed three connecting links, and are suitable to normal packaging method because of easy dividing into 2 (n>1) nodes. The apparatuses comprise the following nodes. The first node has three links connected to other nodes respectively. The second node has three links, one links of them is connected to the first node, and the other two links are in charge of connection of X&plus; direction, X&minus; direction. The third node has three links, one link of them is connected to the first node, and the other two links are in charge of connection of Y&plus; direction, Y&minus; direction. The fourth node has three links, one link of them is connected to the first node, and the other two links are in charge of connection of Z&plus; direction, Z&minus; direction.

Apparatus and method for interconnecting 3-link nodes and parallel processing apparatus using the same

An apparatus for controlling a cache in a computing node, which is located between a node bus and an interconnection network to perform a cache coherence protocol, includes: a node bus interface for interfacing with the node bus; an interconnection network interface for interfacing with the interconnection network; a cache control logic means for controlling the cache to perform the cache coherence protocol; bus-side dual-port transaction buffers coupled between said node bus interface and said cache control logic means for buffering transaction requested and replied from or to local processors contained in the computing node; and network-side dual-port transaction buffers coupled between said interconnection network interface and said cache control logic for buffering transaction requested and replied from or to remote processors contained in another computing node coupled to the interconnection network.

Apparatus for controlling cache by using dual-port transaction buffers

The present invention relates to a routing control apparatus for performing a round robin arbitration and an adaptive routing control. The present invention relates to a routing controller for performing an arbitration and a routing control which are nucleus functions of the crossbar routing switch and, in particular, to a normal routing controller unit for performing a priority based round robin arbitration and an adaptive routing controller unit for performing an adaptive routing control by adding an adaptive routing switch logic to the normal routing controller.

Adaptive routing controller of a crossbar core module used in a crossbar routing switch

There is disclosed a node booting method in a high-speed parallel computer. Other than the method in which the system using a conventional network down loads the operating system kernel image from the boot server, the method according to the present invention provides an environment by which a boot can be progressed in parallel and a boot progress state can be monitored through a console terminal, thus improving a boot speed. The node booting method according to the present invention is comprised of a first step of finding a logical boot path using a node construction table managed by a firmware; a second step of determining boot subject nodes so that copy of an operating system kernel image can be made simultaneously; a third step of copying effective portions of the operating system loaded at the memories onto the subject nodes; a fourth step of informing a boot node of the node state and to display the boot progress state on a console terminal at the start and end time of the booting; and a fifth step of simultaneously starting execution at the remaining portions of the copied operating system when the kernel image are completely copied onto all the nodes.

Node booting method in high-speed parallel computer

The present invention relates to a structure of processor having a plurality of main processors and sub processors, and a method for sharing the sub processors, wherein a method is used for preserving a state of a register file by using a shadow register file when main processor inputs an instruction of the sub processor in case that an exceptional situation happens under processing of an instruction of sub processor and for rolling back thereafter the preserved state in case there is an information of occurrence of the exceptional situation from the sub processor. Also, in order to solve a problem that cache efficiency is reduced due to the use of a first cache which is relatively small and frequently used, there is suggested a first cache bypassing function. Further, in order to solve a problem that its processing speed is reduced when the main processor transfers instructions in sub processor, it is possible to improve the processors' parallelism and its efficiency by providing an extra register file.

Structure of processor having a plurality of main processors and sub

The present invention relates to the fast destaging method using a parity engine, and more particularly to the fast destaging method for constituting and administering the cache of disk array in order to minimize lowering of write performance which occurs in high-speed disk array controller using VRAM parity engine. According to the invention, the disk cache is composed of the read cache, the write cache and the destaging cache. The write caching is processed as being divided into the write cache and the destaging cache. The destaging cache, which has just one more block for mid parity to its data block, uses less memory and enables the write cache to be allocated with more blocks, and thereby it can improve hit ratio of cache. Write requests are first stored on the write cache, and if the write cache is full, they move blocks that would be least used thereafter into the destaging cache. Once destaging is requested, it is practicable with one parity calculation and two write operations by selecting blocks that is least recently used. Also in destaging, block parity calculation can increase its speed and relieve the processor burden by using a VRAM based parity engine which has its dual ports.

Fast destaging method using parity engine

The present invention relates to a message-passing computer system and a packet-switched interconnection network. The message transfer apparatus in a packet-switched interconnection network includes a message send controller controlling a send procedure in which messages requested by a processor are sent via an output port, and a timer enabled by an output signal of the message send controller and generating a timeout signal. A buffer unit is connected to the message send controller and is composed of a message buffer having four buffers and a data buffer. A local bus controller connects the message send controller and the buffer unit to the local bus and controls a transfer request and a transfer response to the local bus. An output port controller connected to both the message send controller and the buffer unit controls the output port which sends a packet to an interconnection network.

Growing community of inventors

Taejon, South Korea

Suk Han Yoon