Intel Corporation

Nvidia Corporation

Sujoyita Kaushikkar

Wishwesh Anil Gandhi

Mark Hairgrove

Karan Mehra

Liang Yin

Alexey Suprun

Kermin ChoFleming

Krishna N Vinod

Ping Zou

Bhavya K Daya

Sami Olavi Johannes Kiminki

Daniel Glenn Robinson

Aniket S Kakade

Anup Holey

Alexander Michael Waterman

Jeff Smith

A processing device including a first cache is coupled to a system memory and a parallel processing unit (PPU) including a second cache. An operation to modify cache lines of the second cache associated with a first aperture of the system memory is received. A first subset of cache lines of the second cache is identified. The first subset of cache lines is associated with the first aperture of the system memory and is different from a second subset of cache lines of a second aperture of the system memory. The first subset of cache lines is modified as specified by the cache operation.

Systems and methods for aperture-specific cache operations

Systems, methods, and apparatuses relating to arbitration among a plurality of memory interface circuits in a configurable spatial accelerator are described. In one embodiment, a configurable spatial accelerator (CSA) includes a plurality of processing elements; a plurality of request address file (RAF) circuits, and a circuit switched interconnect network between the plurality of processing elements and the RAF circuits. As a dataflow architecture, embodiments of CSA have a unique memory architecture where memory accesses are decoupled into an explicit request and response phase allowing pipelining through memory. Certain embodiments herein provide for improved memory sub-system design via arbitration and the improvements to arbitration discussed herein.

Apparatuses, methods, and systems for memory interface circuit arbitration in a configurable spatial accelerator

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San Jose, CA, United States of America

Sujoyita Kaushikkar