Xilinx, Inc.

Sujoy Mitra

L James Hwang

Ralph D Wittig

Sundararajarao Mohan

Eric F Dellinger

Cameron D Patterson

The invention provides parametric modules called Self Implementing Modules (SIMs) for use in programmable logic devices such as FPGAS. The invention further provides tools and methods for generating and using SIMs. SIMs implement themselves at the time the design is elaborated, targeting a specified FPGA according to specified parameters. In one embodiment, a SIM references or includes one or more floorplanners each of which may employ one or more placement algorithms. Such placement algorithms might include, for example: a linear ordering algorithm that places datapath logic bitwise in a regular linear pattern; a rectangular mesh algorithm that implements memory in a grid pattern in distributed RAM; a columnar algorithm for counters and other arithmetic logic; or a simulated annealing algorithm for random logic such as control logic. Therefore, a design including more than one SIM can utilize a plurality of placement algorithms at the same or different levels of hierarchy. The design as a whole can therefore utilize a non-uniform global placement strategy.

Hetergeneous method for determining module placement in FPGAs

A method is provided for structured layout of design objects in a hardware description language (HDL). Standard features of the HDL are used to specify a first-level design object and the placement of other design objects in the first-level design object. A first-level design object is declared, wherein the first design object has no input or output ports and has one or more slots available for one or more second-level design objects. Values are assigned to attributes of the first-level design object to indicate placement for the second-level design objects within the first-level design object. The second-level design objects are declared as elements within the first-level design object, and the first- and second-level design objects are thereafter compiled.

Method for structured layout in a hardware description language

The invention provides parametric modules called Self Implementing Modules (SIMs) for use in programmable logic devices such as FPGAs. The invention further provides tools and methods for generating and using SIMs. SIMs implement themselves at the time the design is elaborated, targeting a specified FPGA according to specified parameters that may, for example, include the required timing, data width, number of taps for a FIR filter, and so forth. SIMs are called &ldquo;self implementing&rdquo; because they encapsulate much of their own implementation information, including mapping, placement, and (optionally) routing information. Therefore, implementing a SIM-based design is significantly faster than with traditional modules, since much of the implementation is already complete and incorporated in the SIM.

Context-sensitive self implementing modules

The invention provides parametric modules called Self Implementing Modules (SIMs) for use in programmable logic devices such as FPGAs. The invention further provides tools and methods for generating and using SIMs. SIMs implement themselves at the time the design is elaborated, targeting a specified FPGA according to specified parameters. In one embodiment, a SIM automatically places and interconnects child SIMs in a mesh pattern. The mesh is a 2-dimensional object corresponding to an array of CLBs on an FPGA. In essence, this embodiment allows a SIM to reserve routing resources on a target device (e.g., an FPGA), and allocate these resources to its child SIMs. Using a defined protocol, each child SIM can request and reserve routing resources, as well as placement resources (such as flip-flops and function generators in the CLBs) through the parent SIM. The routing resources are not necessarily limited to local or nearest neighbor routing.

Method for specifying routing in a logic module by direct module communication

The invention provides parametric modules called Self Implementing Modules (SIMs) for use in programmable logic devices such as FPGAs. The invention further provides tools and methods for generating and using SIMs. SIMs implement themselves at the time the design is elaborated, targeting a specified FPGA according to specified parameters. In one embodiment, a SIM references or includes one or more floorplanners each of which may employ one or more placement algorithms. Such placement algorithms might include, for example: a linear ordering algorithm that places datapath logic bitwise in a regular linear pattern; a rectangular mesh algorithm that implements memory in a grid pattern in distributed RAM; a columnar algorithm for counters and other arithmetic logic; or a simulated annealing algorithm for random logic such as control logic. Therefore, a design including more than one SIM can utilize a plurality of placement algorithms at the same or different levels of hierarchy. The design as a whole can therefore utilize a non-uniform global placement strategy.

Heterogeneous method for determining module placement in FPGAs

The invention supplies a method whereby placement information for elements of a logic module is specified in such a manner that specific coordinates need not be included. This method can be applied to any module or other element having an associated placement in a programmable device. Using the method of the invention, relative coordinates (such as the RLOC constraints discussed in relation to the prior art) need not be specified. Instead, the invention introduces a vector-based form of layout. Key words or phrases such as &ldquo;COLUMN&rdquo; or &ldquo;ROW&rdquo; indicate the manner in which the elements of the module are to be placed. Use of such parametric words or phrases removes from the module developer the burden of determining exactly how large the module will be for each parameter combination, and in some cases finding expressions by which the relative locations can be calculated.

Method for constraining circuit element positions in structured layouts

The invention provides parametric modules called Self Implementing Modules (SIMs) for use in programmable logic devices such as FPGAs. The invention further provides tools and methods for generating and using SIMs. SIMs implement themselves at the time the design is elaborated, targeting a specified FPGA according to specified parameters that may, for example, include the required timing, data width, number of taps for a FIR filter, and so forth. In one embodiment, the SIM parameters may be symbolic expressions, which may comprise strings or string expressions, logical (Boolean) expressions, or a combination of these data types. The variables in these expressions are either parameters of the SIM or parameters of the &ldquo;parent&rdquo; of the SIM. Parametric expressions are parsed and evaluated at the time the SIM is elaborated; i.e., at run-time, usually when the design is mapped, placed, and routed in a specific FPGA. The use of parametric expressions interpreted at elaboration time allows dynamic inheritance and synthesis of actual parameter values, rather than the static value inheritance commonly found in programming languages such as C&plus;&plus; and Java.

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Cupertino, CA, United States of America

Sujoy Mitra