Texas Instruments Corporation

Silab Tech Pvt. Ltd.

Sujoy Chakravarty

Sumantra Seth

Jayawardan Janardhanan

Somasunder Kattepura Sreenath

Biman Chattopadhyay

Ravi Mehta

Vikas Kumar Sinha

Gopalkrishna Nayak

Karthik Subburaj

Krishnaswamy Nagaraj

Anant Shankar Kamath

Jagdish Chand Goyal

Samala Sreekiran

Sudheer Kumar Vemulapalli

Abhijith Arakali

Shivaprakash Halagur

Pentakota A Visvesvaraya

Bharathi Rahuldev Holla

Arakali Abhijith

Embodiments of the present invention disclose an apparatus for managing clock duty cycle. The apparatus comprises a Duty Cycle Control Circuit (DCCC) for receiving at least an input clock signal and generating an output clock signal with adjustable duty cycle, a first Low-Pass Filter with Pull-Up Resistor (LPFPR) for receiving the output clock signal with adjustable duty cycle and simultaneously averaging and raising the common mode of the output thereof, a frequency divider for generating a signal with a 50% duty cycle, a second LPFPR for receiving the generated signal with 50% duty cycle and simultaneously averaging and raising the common mode of the output thereof and an OPAMP for receiving the outputs of the first and second LPFPRs for generating an equivalent reference signal to be fed to the DCCC as a control input, thereby facilitating correction of the duty cycle of the input clock signal.

Apparatus for managing clock duty cycle correction

A system and method for managing estimation and calibration of non-ideality of a Clock and Data Recovery circuit includes phase interpolators (PIs), first and second sets of delay elements, and a clock delay element. A first delay element of the first set of delay elements is programmed using a first digital delay control code (DDCC). The clock delay element is calibrated using a digital external delay control code (DEDCC) till a predetermined criterion is met, and is retained for subsequent use. The remaining delay elements of the first set of delay elements are separately calibrated based on the DEDCC. A first delay element of the second set of delay elements is programmed using a second DDCC. The DEDCC is readjusted for the second set of delay elements. The remaining delay elements of the second set of delay elements are separately calibrated based on the readjusted DEDCC.

Method and apparatus for managing estimation and calibration of non-ideality of a phase interpolator (PI)-based clock and data recovery (CDR) circuit

A clock and data recovery module (CDR) is configured to perform fast locking using only two samples per each unit interval (UI). Two clock phase signals are selected from a plurality of clock phase signals. A sequence of data bits is sampled at a rate of two times per UI responsive to the two clock phase signals in which a first sample of each UI is designated as an edge sample a second sample is designated as a data sample. Each edge sample is voted as early/late as compared to an associated data transition of the sequence of data bits by comparing each edge sample to a next data sample. The sample clocks are locked such that edge samples occur in proximity to data transitions by iteratively adjusting a phase of the two selected clock phase signals by a variable step size in response to the early/late vote.

Fast locking clock and data recovery using only two samples per period

Architecture for VBUS pulsing in an Ultra Deep Sub Micron (UDSM) process for ensuring USB-OTG (On The Go) session request protocol, the architecture being of the type wherein at least a charging circuit is deployed, uses a diode-means connected in a forward path of the charging circuit. The architecture might include a diode-divider including nodes and connected from VBUS in said charging circuit. One embodiment uses both charging and discharging circuits comprising transistors. The charging circuit transistor might comprise a PMOS transistor and the discharging circuit transistor might comprise a NMOS transistor. The architecture might include a three resistance string of a total resistance value approximating 100K Ohms connected between said VBUS and ground, wherein the discharging circuit transistor might comprise a drain extended NMOS transistor. The charging and discharging circuit transistors have VDS and VGD of about 3.6V, whereby high VGS transistors are not needed.

Architecture for VBUS pulsing in UDSM processes

Phase interpolator and a delay circuit for the phase interpolator. The phase interpolator includes a variable delay circuit to rotate phase of an input clock to generate a phase rotated signal. The phase interpolator also includes a delay locked loop coupled to the variable delay circuit to generate a plurality of phase shifted outputs. The delay locked loop includes a plurality of delay elements. Each delay element includes a multiplexer and a delay cell coupled to the multiplexer. The multiplexer is configurable using a first control signal to output one of the phase rotated signal and a phase shifted output of the plurality of phase shifted outputs. The delay cell delays one of the phase rotated signal and the phase shifted output to generate another phase shifted output of the plurality of phase shifted outputs.

Phase interpolator and a delay circuit for the phase interpolator

A fast locking delay-locked loop (DLL), which can also operate as a clock data recovery circuit (CDR), includes a delay chain, a sampling circuit and a transition detector. An input signal and delayed versions of the input signal generated by the delay chain are sampled by the sampling circuit. The outputs of the sampling circuit are provided to a transition detector which selects one of the input signal and its delayed versions determined to have signal transitions most closely aligned with a sampling edge of a clock. The selected signal and the clock are provided as inputs to a phase discriminator which generates an error signal representing a level of phase mismatch between the inputs. The error signal is fed back to the sampling circuit to maintain phase lock between the clock signal and the input bit stream.

Fast-locking delay locked loop

A synchronous circuit for clock multiplexing and output-enable is implemented using a pair of logic gates and an output block. Select signals and enable signals with the corresponding logic sense are provided as inputs to the pair of logic gates, which generate respective logic outputs. The output block contains synchronizers clocked by respective input signals, and receives the logic outputs also as inputs. The output block provides a selected one of the input signals as an output, the provision of the selected input signal being accomplished in a synchronous fashion. Enabling and disabling of the output are also performed synchronously.

Synchronous clock multiplexing and output-enable

A method, apparatus and system of constant output common mode voltage of a pre-amplifier circuit are disclosed. In one embodiment, a system includes a first circuit, a comparator circuit coupled with an output of the first circuit, a pre-amplifier circuit of the comparator circuit, a tracking circuit coupled with a common output location of the pre-amplifier circuit to provide (e.g., source/sink) an additional current to the common output location of the pre-amplifier circuit using an alternate current path in the tracking circuit when an input common mode of the pre-amplifier circuit is beyond a saturation range, and a second circuit of the comparator circuit coupled with the pre-amplifier circuit. A scaled version of a pair of input transistors of a pre-amplifier circuit of the tracking circuit may be created using a scaling factor ('N').

Constant output common mode voltage of a pre-amplifier circuit

The comparator input stage uses low voltage transistors and as the input pair. They have a small threshold voltage, and hence support a low common mode. The circuit includes a current sink coupled to the input pair and ; a first resistor coupled between a first branch of the input pair and a voltage node V ; a second resistor coupled between a second branch of the input pair and the voltage node V ; a first transistor coupled to the voltage node V ; a second transistor having a gate coupled to a gate of the third transistor ; a third resistor coupled to a first end of the second transistor ; and a current source coupled to a second end of the second transistor for controlling a voltage across the third resistor wherein the voltage across the third resistor sets a voltage at the voltage node V . This voltage at the voltage node V serves as an open loop regulation for protection of the input pair transistors and

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Bengaluru, India

Sujoy Chakravarty