Sandisk Technologies Inc.

Western Digital Technologies, Inc.

Sujjatul Islam

Ravi J Kumar

Yu-Chung Lien

Xue Bai Pitner

Sarath Chandran Puthenthermadam

Deepanshu Dutta

Jiahui Yuan

Abhijith Prakash

Muhammad Masuduzzaman

Parth Amin

Md Raquibuzzaman

Longju Liu

Kyeongran Yoo

A memory apparatus includes memory cells and a control means configured to adjust at least one of blind program pulses applied to word lines connected to the memory cells and bit line voltages applied to bit lines coupled to the memory cells in response to determining one of the word lines connected to the memory cells being programmed is susceptible to over-programming. The control means programs non-checkpoint ones of the memory cells associated with a checkpoint state to a verify low voltage for the checkpoint state and programs the non-checkpoint ones of the memory cells to respective non-checkpoint states associated with the checkpoint state by applying the blind program pulses to each non-checkpoint one of the memory cells without verifying whether the non-checkpoint ones of the memory cells have reached their respective non-checkpoint states while applying the bit line voltages to the bit lines associated therewith.

Variable foggy verify levels for selected checkpoint states for non-volatile memory apparatuses

An apparatus includes a control circuit configured connect to non-volatile memory cells. The control circuit is configured to receive a read command directed to data stored in non-volatile memory cells of a first word line and determine that a second word line adjacent to the first word line is sanitized. The control circuit is further configured to select an adjusted read voltage for a read operation directed to the non-volatile memory cells of the first word line based on the determination.

Read schemes with adjustment for neighboring word line sanitization

The memory device includes an array of memory cells, which are configured to retain multiple bits per memory cell, arranged in a plurality of word lines. A controller is configured to program the memory cells of a selected word line in a first programming pass. The first programming pass includes a plurality of programming pulses, each including the application of a programming voltage Vpgm by the controller to a control gate of the selected word line for a first duration. The controller is also configured to further program the memory cells of the selected word line in a second programming pass. The second programming pass includes a plurality of programming pulses, each of which includes the application of a programming voltage Vpgm by the controller to the control gate of the selected word line for a second duration that is different than the first duration.

Variable programming clocks during a multi- stage programming operation in a NAND memory device

The memory device that includes a plurality of memory cells that are arranged in a plurality of word lines. A controller is in electrical communication with the plurality of memory cells. During programming, the controller detects a temperature of the memory device. The controller then programs the memory cells of a selected word line of the plurality of word lines in a plurality of program loops until programming is completed or until the plurality of program loops is greater than a maximum number of program loops. The maximum number of program loops is dependent on the temperature that is detected.

Temperature dependent programming techniques in a memory device

A non-volatile semiconductor memory device, described herein, comprises non-volatile storage elements and one or more control circuits in communication with the non-volatile storage elements. The one or more control circuits are configured to, during a program iteration of a program operation, determine whether a program voltage level of the program iteration exceeds a threshold program voltage level and in response to the determination, identify a set of voltage levels to apply to a source line connected to a set of the non-volatile storage elements. The one or more control circuits are further configured to perform the program iteration of the program operation on the set of non-volatile storage elements, where the program iteration includes applying the set of voltage levels to the source line.

Program voltage dependent program source levels

A non-volatile semiconductor memory device includes non-volatile storage elements and one or more control circuits in communication with the non-volatile storage elements. The one or more control circuits are configured to determine for a program iteration of a program operation on a word line whether a condition is met and in response to determining that the condition is met, identify one or more memory cells of the word line that are in an erased state that have a threshold voltage higher than an erase threshold voltage and perform the program iteration of the program operation. The program iteration includes applying a first bitline inhibit voltage to bitlines connected to the identified one or more memory cells and a second bitline inhibit voltage to bitlines connected to one or more memory cells that are in the erased state that do not have a threshold voltage higher than the erase threshold voltage.

Selective inhibit bitline voltage to cells with worse program disturb

Technology is disclosed herein for detecting grown bad blocks in a non-volatile storage system. A stress test may accelerate stressful conditions on the memory cells and thereby provide for early detection of grown bad blocks. The stress test may include applying a program voltage to a selected word line and a stress voltage that is less than a nominal boosting voltage to a word line adjacent one side of the selected word line. The combination of the program voltage and the stress voltage may generate an e-field that is stronger than an e-field that would be generated in a normal program operation, thereby accelerating the stress on the memory cells. The stress test mat further include programming all of the memory cells to a relatively high threshold voltage, which may create additional stress on the memory cells.

Stress test for grown bad blocks

An apparatus includes one or more control circuits configured to connect to a plurality of non-volatile memory cells through a plurality of word lines. The one or more control circuits are configured to, for each target word line of a plurality of target word lines to be read, select either a first neighboring word line or a second neighboring word line as a selected neighboring word line according to whether non-volatile memory cells of the first neighboring word line are in an erased condition. The one or more control circuits are further configured to determine a read voltage to read non-volatile memory cells of a corresponding target word line according to an amount of charge in non-volatile memory cells of the selected neighboring word line.

Nonvolatile memory with efficient look-ahead read

Apparatuses and techniques are described for reducing the program time for a set of memory cells by using an enhanced step up of a program bias. A program operation includes a first pass in which memory cells are programmed to intermediate states and a second program pass in which the memory cells are programmed from an erased state and the intermediate states to final states. In the first program pass, program time can be reduced by applying an enhanced program bias step up to memory cells of the highest intermediate state in a single program loop, for example. The enhanced program bias step up can be achieved by applying a negative bit line voltage and can be triggered when the memory cells assigned to the second highest intermediate state reach a program milestone such as completing programming.

Reduced program time for memory cells using negative bit line voltage for enhanced step up of program bias

A method for programming a non-volatile memory structure with four-page data, wherein the method comprises, in a first stage, selecting four programmable states of a segment of MLC NAND-type memory cells, programming at least a first of the four programmable states with two pages of a four-page data at a first step voltage level, between programming at least two neighboring programmable states of the four programmable states, increasing the first step voltage level to a second step voltage level for a single program pulse and according to a pre-determined magnitude, and programming a latter of the at least two neighboring programmable states at the first step voltage level.

Growing community of inventors

San Jose, CA, United States of America

Sujjatul Islam