Motorola Corporation

Sujit Sudhaman

Raymond P Voith

Michael R May

Mathew A Rybicki

George P Hoekstra

Matthew A Pendleton

Carlos A Greaves

Howard E Levin

Peter R Molnar

Terence L Johnson

Jeffrey P Gleason

Jody H Everett

Charles D Robinson, Jr

John M Porter

Robin Wiprud

A data interleaving system (20) provides flexibility by performing the interleaving function in a high level controller (32) and a separate low level controller (34). The high level controller (32) receives commands to operate on a codeword basis, in which a codeword is made up of a plurality of symbols which are grouped into a programmable number of frames. The low level controller (34) operates under the direction of the high level controller (32) on a symbol-by-symbol basis. By separating the codeword level tasks from the symbol level tasks, the data interleaving system (20) is able to accommodate various ratios of the number of frames per codeword without significant complexity. An analogous data de-interleaving system (220) includes a high level controller (232) and a low level controller (234).

Systems for programmably interleaving and de-interleaving data and

A transceiver (5) for an asymmetric communication system such as asymmetric digital subscriber line (ADSL) includes a configuration register (71) defining operation at either a central office (CO) or a remote terminal (RT). The configuration register (71) includes a control bit (72) for selecting either CO or RT mode. The transceiver (5) includes a signal processing module (70) configured according to the state of the control bit (72). For example, a digital interface (70) converts transmit data into transmit symbols and converts received symbols into receive data. The digital interface (70) uses a large memory (158) as a buffer in the transmit path and a small memory (160) as a buffer in the receive path in CO mode. In RT mode, the digital interface (70) uses the small memory (160) in the transmit path and the large memory (158) in the receive path. The selective configuration allows a single integrated circuit to be used in both CO and RT equipment.

Single-chip software configurable transceiver for asymmetric

Interleaving/de-interleaving of data is achieved by storing and subsequently retrieving portions of the data from circular buffers (60,70). The circular buffers (60,70) are addressed such that each circular buffer corresponds to an index of data (B.sub.i). Thus, data (80) is written into a circular buffer (60,70) using a first modulo scheme and read using a second modulo scheme, where the second modulo scheme is based on the interleaving scheme. An index array (20) is used to point to the appropriate entry in the circular buffers(60,70) to ensure a proper interleave/de-interleave process.

Method and apparatus for interleave/de-interleave addressing in data

A transceiver (34) includes a rate adaptation buffer (74) that synchronizes a data stream received at a 4.0 kHz rate to a data stream that is transmitted at a 4.05 kHz rate. A transmit section (62) of the transceiver (34) performs rate adaptation using a single rate adaptation buffer. The transmit section (62) includes four autonomous modules which are able to access the data in the rate adaptation buffer (74) independently of one another. These four modules include a CRC-scrambler (72), a FEC encoder (76), an interleaver (78), and a constellation encoder (80). A timing controller (84) prevents contention for accesses to the rate adaptation buffer (74). In addition, each of the four modules perform their respective functions quickly enough to prevent overflow or underflow conditions in the rate adaptation buffer (74). A receive section (64) functions similarly to the transmit section (62).

Rate-adapted communication system and method for efficient buffer

In an ADSL transmitter (62), data is flamed and split between a fast path and an interleave path by multiplexer (66). Data is forward error correction encoded in FEC encoder (70). Data on the interleave path is interleaved by interleaver (72) if an interleave depth (D) is &gt;2. During interleaving, at least one additional read operation is performed, after a series of consecutive write and read operations. The additional read operation permits interleaving to continue without waiting for a next frame of data to arrive at the interleaver. An equal number of additional write operations compensates for the additional reads at a later point. Use of an interleaving memory can also be avoided by turning off or disabling the interleaver, while still permitting data to be sent along the interleave path. Transmit path controller (74) senses if D=1, and if so disables the interleaver and avoids the need for interleaver memory (64).

Method and apparatus for interleaving data in an asymmetric digital

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Austin, TX, United States of America

Sujit Sudhaman