Arm Limited

Sujit Kumar Rout

Vikash

Lalit Gupta

Shri Sagar Dwivedi

Vivek Nautiyal

Jitendra Dasani

Pradeep Raj

Akash Bangalore Srinivasa

Gaurav Rattan Singla

Manish Trivedi

Arjunesh Namboothiri Madhavan

Rejeesh Ammanath Vijayan

Neelima Gudipati

Various implementations described herein are directed to an integrated circuit having memory circuitry with an array of bitcells. The integrated circuit may include read-write circuitry that is coupled to the memory circuitry to perform read operations and write operations for the array of bitcells. The integrated circuit may include write assist circuitry that is coupled to the memory circuitry and the read-write circuitry. The write assist circuitry may receive a control signal from the read-write circuitry. Further, the write assist circuitry may sense write operations based on the control signal and may drive the write operations for the array of bitcells.

Write assist circuitry

Various implementations described herein are directed to an integrated circuit for read-write contention. The integrated circuit may include a memory circuit having multiple ports configured to receive data signals corresponding to each port. The integrated circuit may include a contention override circuit providing a contention override signal for each port based on detecting a read-write contention between the ports. The integrated circuit may include a write circuit having multiple passgates for each port including write passgates and contention passgates for each port. The write passgates may be input with data signals from corresponding ports. The contention passgates may be input with data signals from opposing ports based on opposing contention override signals.

Read-write contention circuitry

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Bengaluru, India

Sujit Kumar Rout