Samsung Electronics Co., Ltd.

Sujin Jung

Jinbum Kim

Sunguk Jang

Youngdae Cho

Choeun Lee

Byeongchan Lee

Seokhoon Kim

Yang Xu

Kwan Heum Lee

Kang Hun Moon

Kihwan Kim

Jinwoo Kim

Ingyu Jang

Dahye Kim

Bonyoung Koo

Kwanheum Lee

Chul Kyu Kim

Dongsuk Shin

Sangmoon Lee

Nam-Kyu Kim

Jungtaek Kim

Sihyung Lee

Junbeom Park

Jongryeol Yoo

Iksu Jung

Jeongho Yoo

Minseok Shin

Changhwan Lee

Heejun Park

Sunyoung Lee

Sungjin Park

Dongwoo Kim

Seung Hun Lee

Youngjin Cho

Ki Hwan Kim

Gyeom Kim

Pankwi Park

Dong Chan Suh

Jin Bum Kim

Hyunjae Kang

Hanki Lee

Kyung Yub Jeon

Jinyeong Joe

Jaeyoung Park

Dongmyoung Kim

Haegeon Jung

Changwoo Jung

Kanghun Moon

Sangpil Lee

Hyunmin Oh

Yonghan Lee

Seungkwon Choi

Yongjun Nam

Hakrae Kang

Jieon Yoon

Changjin Yang

Kyoungjong Kim

A semiconductor device includes a fin-type active region that protrudes from a substrate and extends in a first direction, a plurality of channel layers on the fin-type active region that are spaced apart from each other in a second direction that is perpendicular to an upper surface of the substrate, a gate structure that intersects the fin-type active region, extends in the second direction, and surrounds each of the plurality of channel layers in a third direction, fence spacers on side surfaces of the fin-type active region in the second direction on sides of the gate structure and extending in the second direction, and a source/drain region between the fence spacers on the fin-type active region at sides of the gate structure, connected to each of the plurality of channel layers, and having voids in side surfaces adjacent the fence spacers.

Semiconductor device

An electronic device is provided. The electronic device includes a housing, a display disposed inside the housing, the display disposed in a first direction so that a screen of the display is exposed to an outside of the housing, a first printed circuit board (PCB) disposed inside the housing, a flexible printed circuit board (FPCB) disposed inside the housing and including a first portion adjacent to the display and a third portion extending from the first portion and electrically connected with the first PCB, a first guide member disposed inside the housing, and a second guide member disposed inside the housing. At least a portion of the third portion may be disposed to pass between the first guide member and the second guide member. The at least the portion of the third portion may be provided with force in a second direction opposite to the first direction by the first guide member.

Electronic device including display

A semiconductor device includes a substrate having an active region extending in a first direction; a gate structure disposed on the substrate, intersecting the active region, and extending in a second direction; channel layers disposed on the active region to be spaced apart from each other in a third direction, perpendicular to an upper surface of the substrate, and to be surrounded by the gate structure; source/drain regions disposed on both sides of the gate structure and connected to the channel layers; air gap regions located between the source/drain regions and the active region and spaced apart from each other in the third direction; and semiconductor layers alternately disposed with the air gap regions in the third direction and defining the air gap regions, wherein lower ends of the source/drain regions are located on a level lower than an uppermost air gap region.

Semiconductor device including air gap regions below source/drain regions

Disclosed are a semiconductor device and a method of fabricating the same, the semiconductor device including an active pattern on a substrate, a source/drain pattern on the active pattern, a channel pattern on the active pattern, connected to the source/drain pattern, and including stacked semiconductor patterns, a gate electrode extending in a first direction and crossing the channel pattern, and a gate insulating layer between the gate electrode and the channel pattern. The source/drain pattern includes first and second semiconductor layers, the first semiconductor layer including a center portion including a second outer side surface in contact with the gate insulating layer and an edge portion adjacent to a side of the center portion and including a first outer side surface in contact with the gate insulating layer. The second outer side surface is further recessed toward the second semiconductor layer, compared with the first outer side surface.

Multi-oxide-semiconductor field-effect transistor with stacked source/drain structure

A semiconductor device includes an active region extending in a first direction on a substrate, a plurality of channel layers vertically spaced apart from each other on the active region and including a semiconductor material, a gate structure extending in a second direction on the substrate, and a source/drain region disposed on the active region on at least one side of the gate structure. The gate structure intersects the active region and the plurality of channel layers, and surrounds the plurality of channel layers. The source/drain region contacts the plurality of channel layers and includes first impurities. In at least a portion of the plurality of channel layers, a lower region adjacent to the active region includes the first impurities and second impurities at a first concentration, and an upper region includes the first impurities and the second impurities at a second concentration lower than the first concentration.

Semiconductor devices

An integrated circuit (IC) device includes a fin-type active region extending longitudinally in a first lateral direction on a substrate. A nanosheet is apart from a fin top surface of the fin-type active region in a vertical direction. An inner insulating spacer is between the substrate and the nanosheet. A gate line includes a main gate portion and a sub-gate portion. The main gate portion extends longitudinally in a second lateral direction on the nanosheet. The sub-gate portion is integrally connected to the main gate portion and between the substrate and the nanosheet. A source/drain region is in contact with the inner insulating spacer and the nanosheet. The source/drain region includes a single crystalline semiconductor body and at least one lower stacking fault surface linearly extending from the inner insulating spacer through the single crystalline semiconductor body.

Integrated circuit device

A semiconductor device, including a silicon on insulator (SOI) substrate is disclosed. The device may include gate structures formed on the SOI substrate and being spaced apart from each other in a horizontal direction, and a plurality of channels spaced apart from each other in a vertical direction. Each of the channels may extend through each of the gate structures in the horizontal direction. The device may include a seed layer and a source/drain region. The source/drain region may be connected to the channels, and each sidewall of the source/drain region in the horizontal direction may have a concave-convex shape. The device may include a protruding portion of the source/drain region formed between the gate structures that protrudes in the horizontal direction compared to a non-protruding portion of the source/drain region formed between the channels.

Method of forming a semiconductor device with a seed layer migration process

A semiconductor device including: an active pattern on a substrate, the active pattern including a recess, the recess having a 'V' shape; a growth prevention pattern on the recess; gate structures on portions of the active pattern at opposite sides of the recess; channels spaced apart from each other in a vertical direction perpendicular to an upper surface of the substrate, each of the channels extending through one of the gate structures; and a source/drain layer on the growth prevention pattern, the source/drain layer contacting the channels.

An integrated circuit (IC) device includes a fin-type active region on a substrate. A mesa-type channel region protrudes from the fin-type active region in a vertical direction. The mesa-type channel region is integrally connected with the fin-type active region. A gate line substantially surrounds a mesa-type channel region on the fin-type active region. A gate dielectric film is between the mesa-type channel region and the gate line. The mesa-type channel region includes: a plurality of round convex portions, which are convex toward the gate line; a concavo-convex sidewall, which includes a portion of each of the plurality of round convex portions and faces the gate line; and at least one void, which is inside the mesa-type channel region.

Integrated circuit devices

An electronic device is provided. The electronic device includes a housing including a support member and a rear plate, a camera support member disposed between the support member and the rear plate, a camera module disposed on the support member, a camera window covering at least a part of the camera module, and a compression member disposed between the camera window and the camera module. The camera module may include a first area facing the camera support member, a second area facing the compression member, and a third area facing the camera window and at least partially surrounded by the compression member.

Electronic device including camera module

A semiconductor device includes a channel, a first source/drain structure on a first side surface of the channel, a second source/drain structure on a second side surface of the channel, a gate structure surrounding the channel, an inner spacer layer on a side surface of the gate structure, and an outer spacer layer on an outer surface of the inner spacer layer. The first source/drain structure includes a first source/drain layer on the channel and a second source/drain layer on the first source/drain layer, and on a plane of the semiconductor device that passes through the channel, at least one of a first boundary line of the first source/drain layer in contact with the second source/drain layer and a second boundary line of the first source/drain layer in contact with the channel may be convex, extending toward the channel.

A semiconductor device includes an active region on a substrate extending in a first direction, the active region having an upper surface and sidewalls, a plurality of channel layers above the active region to be vertically spaced apart from each other, a gate electrode extending in a second direction to intersect the active region and partially surrounding the plurality of channel layers, and a source/drain region on the active region on at least one side of the gate electrode and in contact with the plurality of channel layers, and extending from the sidewalls of the active region having a major width in the second direction in a first region adjacent to a lowermost channel layer adjacent to the active region among the plurality of channel layer.

A semiconductor device may include semiconductor patterns, a gate structure, a first spacer, a first semiconductor layer and a second semiconductor layer. The semiconductor patterns may be formed on a substrate, and may be spaced apart from each other in a vertical direction perpendicular to an upper surface of the substrate and may overlap in the vertical direction. The gate structure may be formed on the substrate and the semiconductor patterns. At least portion of the gate structure may be formed vertically between the semiconductor patterns. The first spacer may cover opposite sidewalls of the gate structure, the sidewalls opposite to each other in a first direction. The first semiconductor layer may cover the sidewalls of the semiconductor patterns in the first direction, and surfaces of the first spacer and the substrate. The first semiconductor layer may have a first concentration of impurities. The second semiconductor layer may be formed on the first semiconductor layer, and may have a second concentration of impurities different from the first concentration of impurities. The semiconductor device may have good characteristics and high reliability.

Semiconductor devices and methods of manufacturing the same

According to an embodiment of the present invention, an electronic device may comprise: a housing; a printed circuit board disposed inside the housing, the printed circuit board comprising a first surface, a second surface facing away from the first surface, and a first through-hole and a second through-hole penetrating the first surface and the second surface; a first microphone disposed on the second surface so as to at least partially overlap the first through-hole when seen from above the first surface; a second microphone disposed on the second surface so as to at least partially overlap the second through-hole when seen from above the first surface; a support member disposed on the first surface, the support member comprising a third surface facing the first surface, a fourth surface facing away from the third surface, a third through-hole at least partially overlapping the first through-hole when seen from above the first surface, and a fourth through-hole at least partially overlapping the second through-hole when seen from above the first surface; a first sound-transmitting member disposed on the fourth surface so as to at least partially overlap the third through-hole; and a second sound-transmitting member disposed on the fourth surface so as to at least partially overlap the fourth through-hole. Various other embodiments may be included.

Electronic device comprising multiple microphones

Growing community of inventors

Hwaseong-si, South Korea

Sujin Jung