International Business Machines Corporation

Oracle International Corporation

Sujeet Kumar

Anand B Arunagiri

Viresh Paruthi

Udo Krautz

Angelo Pruscino

Pradeep Kumar Nalla

Raj Kumar Gajavelly

Sunil Kumar

Anuj Tripathi

Macharapu Sai Prasanth

Joy Mukherjee

Disclosed aspects relate to verifying an integrated circuit design. A set of design constraints may be received with respect to a verification process for the integrated circuit design. Based on the set of design constraints, a constraint model may be constructed. A new global constraint may be determined using the constraint model. The new global constraint may be used to process the verification process for the integrated circuit design.

Integrated circuit design verification

A tool for formally verifying forwarding paths in an information pipeline. The tool creates two logic design copies of the pipeline to be verified. The tool retrieves a first and a second instruction, which have previously been proven to compute a mathematically correct result when executed separately. The tool defines driver input functions for issuing instructions to the two logic design copies. In accordance with the driver input functions, the tool issues instructions to the two logic design copies. The tool abstracts data flow of the two logic design copies to isolate forwarding paths for verification. The tool adjusts for latency differences between the first and second logic design copies. The tool checks a register for results, and when results from of two logic design copies become available in the register, the tool verifies the results to conclusively prove the correctness of all states of the information pipeline.

Verifying forwarding paths in pipelines

A system, method, and computer program product are described for distinguishing between a computing system that is hung in a hang state and systems that are in an idle or otherwise non-hang state which do not need intervention before regaining the ability to adequately process work. According to some approaches, heuristics are employed to perform hang and idle system detection and validation. Data representative of systems resources are analyzed and transformed in order to identify systems that are in a hang state.

Method, system, and computer program product for determining a hang state and distinguishing a hang state from an idle state

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Bengaluru, India

Sujeet Kumar