Intel Corporation

Sujal A Vora

Krishnakanth Venkata Sistla

Ankush Varma

John Joseph Browne

Vivek Garg

Chris MacNamara

Vasudevan Srinivasan

Ian M Steiner

Nagasubramanian Gurumoorthy

Venkatesh Ramamurthy

Nikhil Gupta

Corey D Gough

William Johnson Bowhill

Ripan Das

David P Lerner

Joseph M Sullivan

Aurobindo Dasgupta

A processing device includes a plurality of processing cores, a control register, associated with a first processing core of the plurality of processing cores, to store a first base clock frequency value at which the first processing core is to run, and a power management circuit to receive a base clock frequency request comprising a second base clock frequency value, store the second base clock frequency value in the control register to cause the first processing core to run at the second base clock frequency value, and expose the second base clock frequency value on a hardware interface associated with the power management circuit.

Configuration of base clock frequency of processor based on usage parameters

Systems, methods, and apparatuses relating to enhanced matrix multiplier architecture are described. In one embodiment, an apparatus includes a matrix operations accelerator circuit having a two-dimensional grid of multiplier circuits; a first plurality of registers that represents a first two-dimensional matrix coupled to the matrix operations accelerator circuit; a second plurality of registers that represents a second two-dimensional matrix coupled to the matrix operations accelerator circuit; a decoder, of a core coupled to the matrix operations accelerator circuit, to decode a single instruction into a decoded single instruction; and an execution circuit of the core to execute the decoded single instruction to store each element of the first two-dimensional matrix from the first plurality of registers into a respective clocked flip-flop circuit of each multiplier circuit of the two-dimensional grid of multiplier circuits, store a first element of a first proper subset of elements of the second two-dimensional matrix from the second plurality of registers into a single first clocked flip-flop circuit coupled to a first proper subset of multiplier circuits of the two-dimensional grid of multiplier circuits, store a second element of the first proper subset of elements of the second two-dimensional matrix from the second plurality of registers into a single second clocked flip-flop circuit coupled to a second proper subset of multiplier circuits of the two-dimensional grid of multiplier circuits, multiply the first element of the first proper subset of elements from the single first clocked flip-flop circuit by a respective element from the clocked flip-flop circuit of each multiplier circuit of the first proper subset of multiplier circuits to generate a first plurality of resultants, and multiply the second element of the first proper subset of elements from the single second clocked flip-flop circuit by a respective element from the clocked flip-flop circuit of each multiplier circuit of the second proper subset of multiplier circuits to generate a second plurality of resultants.

Apparatuses, methods, and systems for enhanced matrix multiplier architecture

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San Jose, CA, United States of America

Sujal A Vora