Sanyo Electric Co., Ltd.

Suichi Kikuchi

Masaaki Momen

Eiji Nishibe

The semiconductor device of this invention has a P type well region formed inside a P type semiconductor substrate, on which at least three gate insulating films each having a different thickness are formed. Also, the device has the gate electrode formed extending over the three gate insulating films. The ion implantation of the impurity for controlling the threshold voltage is performed only under the thinnest gate insulating film of the three gate insulating films.

Semiconductor device and manufacturing method thereof

A die size is reduced in a semiconductor device which has a gate electrode formed on a first gate insulation film and a second gate insulation film, source and drain regions (N&minus; layers and N&plus; layers) formed adjacent to the gate electrode and a channel region, wherein at least the gate electrode, the channel region and the source and drain regions are polygonal in shape.

Semiconductor device

A die size is reduced in a semiconductor device having a gate electrode formed on a first gate insulation film and a second gate insulation film, source and drain regions (N&minus; layers and N&plus; layers) formed adjacent to the gate electrode and a channel region, wherein the gate electrode, the channel region and the source and drain regions are hexagonal. Neighboring transistors are displaced from each other by a predetermined distance.

Polygonal structure semiconductor device

A semiconductor device having a P type well region formed inside a P type semiconductor substrate, on which at least three gate insulating films each having a different thickness are formed. Also, the device has the gate electrode formed extending over the three gate insulating films. The ion implantation of the impurity for controlling the threshold voltage is performed only under the thinnest gate insulating film of the three gate insulating films.

Growing community of inventors

Oizumi-machi, Japan

Suichi Kikuchi