Synopsys, Inc.

Sui Zheng

Jun Wang

Cheng-Ming Wu

Jun Zhu

Hu Cai

Yun-Jui Li

Yuting Fu

Hwei-Tseng Wang

Yu Fan Lu

Jeong-Tyng Li

Techniques and systems for implementing a general extensible layer mapping approach that maps between integrated circuit (IC) design database layers and process layers are described. A first IC design layout having in-design layers can be converted into a second IC design layout having derived layers, wherein said converting comprises mapping the in-design layers to the derived layers by applying a set of layer derivation rules to shapes in the IC design layout, and wherein the set of layer derivation rules implements a one-to-many mapping between the in-design layers and the derived layers. Next, a one-to-one mapping between the derived layers and process layers used in a parasitic extraction tool can be generated. Parasitic extraction on the IC design layout then be performed by providing the second IC design layout and the one-to-one mapping to the parasitic extraction tool.

Extensible layer mapping for in-design verification

Growing community of inventors

Shanghai, China

Sui Zheng