Lg Display Co., Ltd.

Suhyuk Jang

Woongki Min

Yonggi Son

Jongwoo Kim

Hongsung Song

Hyojin Kim

Jinwon Lee

Sungjo Koo

Hwanjoo Lee

Hyuntaek Nam

Hong Sung Song

HyeJin Kim

MyungKook Moon

Songjae Lee

Jeonga Lee

Chaeyoul Cho

Youngho Kim

Jinsung Kim

Sungsu Han

JaeWoo Lee

Yangseok Jeong

Jiwoong Park

Jincheol Hong

Sungwan Hong

Hoonbae Kim

Semin Kung

DaSol Jun

Seokjun Kang

Junhwan Park

Donghoon Cha

A channel control unit and a display device using the same are provided. The channel control unit can include a data driver that converts pixel data into data voltages and supplies the data voltages to data lines, and an ineffective channel controller that receives channel data, generates dummy data during an ineffective channel section indicated by the channel data, and sends the dummy data to the data driver.

Channel controller and display device using the same

A memory protection device for protecting information stored in a memory includes a transmission block processing transmission data including state information of a display panel to generate original data in compliance with a transmission interface standard, an encoding unit connected to an output terminal of the transmission block and modulating a portion of the original data so as to be different from an original value to generate encoding data, and an inputoutput controller writing the encoding data into the memory according to the transmission interface standard.

Memory protection device and method and organic light emitting display device including the same

An organic light emitting display device which improves expression capability in a low luminance level region, wherein, when receiving a pulse width modulation value indicating a low luminance level region, the device changes the received pulse width modulation value into a pulse width modulation dimming value indicating a high luminance level region, and expresses a low luminance level region through a luminance level indicated by the pulse width modulation dimming value and a pulse width modulation dimming operation. Luminance in a low luminance level region is controlled through a pulse width modulation dimming value indicating a high luminance level region and a pulse width modulation dimming operation, so that it is possible to minutely control luminance in a low luminance level region and improve expression capability in a low luminance level region.

Organic light emitting display device, data driver, and method for driving data driver

Disclosed are an organic light emitting display and a method of driving the same. A charging circuit supplies charging voltages to organic light emitting diodes included in the plurality of subpixels, wherein a different charging voltage is supplied to at least one of the organic light emitting diodes. The data driver supplies data signals to data lines of the plurality of subpixels.

Organic light emitting display (OLED) and method of driving the same

Provided are a display device and a method of controlling a power integrated circuit (PIC) thereof. The display device in one embodiment includes a controller for generating a switch pulse signal synchronized with an input image and initializing the switch pulse signal during a frame blank period in which the input image is not present; and a power integrated circuit (PIC) driven according to the switch pulse signal to generate power of a display panel. A duty ratio of the switch pulse signal is aligned to be greater than 0 and equal to or less than 3% during an alignment period set within a frame blank period, compared with a normal period. Thus, a change in the duty ratio of the switch pulse signal within the frame blank period is controlled to be minimized to prevent a degradation of image quality due to the variation of power.

Display device and method of controlling power integrated circuit

A display device is disclosed in which a luminance control device includes a temperature sensor that detects a temperature of a display device; an average picture level part that calculates an average picture level, which defines an average brightness of an image input into the display device; and a luminance control part that generates a temperature-dependent peak luminance, which varies with temperature and average picture level, based on a top gain curve defining how a maximum luminance decreases as the temperature of the display device rises and a bottom gain curve defining how a minimum luminance decreases as the temperature of the display device rises, wherein the luminance control part fixes the temperature-dependent peak luminance at a specific luminance level, regardless of changes in average picture level, at a specific temperature in a high-temperature range which is higher than a room-temperature range.

Luminance control device and display device comprising the same

A display device and a method for driving the same are discussed. The display device, in which pixels of a display panel are charged to a data voltage during a pixel driving period and touch sensors embedded in the display panel are driven during a touch sensor driving period, includes a timing controller which transmits a preamble signal, control data, and data of an input image to a source driver integrated circuit (IC) during the pixel driving period and transmits the preamble signal to the source driver IC during the touch sensor driving period.

Display device and method for driving the same during display period and touch period of display device

A power control device includes a temperature sensing unit sensing a temperature of a display panel and outputting a temperature sensing value, a timing controller generating a power control signal, and a power management integrated circuit (PMIC) adjusting a voltage level of high potential driving power to be applied to the display panel on a basis of the power control signal. When a voltage level of VDDEL is adjusted using a S-wire interface scheme, VDDEL is adjusted when the power control signal satisfies a preset condition, whereby an influence of noise is excluded and a stable output may be obtained.

Power control device and method and organic light emitting display device including the same

The exemplary embodiment relates to a liquid crystal display device. The liquid crystal display according to the exemplary embodiment includes: a liquid crystal display panel on which a plurality of data lines cross a plurality of gate lines, wherein each data line and each gate line is connected to a thin film transistor; a source drive IC supplying data voltages to the data lines; a gate drive IC supplying gate pulses to the gate lines; a system board equipped with a scaler that transmits data from the scaler through an interface that comprises 4-pair of data transmitting lines; and a control board equipped with a timing controller that receives the data through the interface and supplies the data to the source drive IC and controls the operating timing of the source drive IC and the gate drive IC.

Liquid crystal display

A liquid crystal display and a driving method thereof are provided. The liquid crystal display includes a liquid crystal display panel, a register for storing pixel information of a problem pattern and polarity pattern information, a block pattern recognition unit for comparing input data with the problem pattern to count the number of problem patterns contained in the input data and comparing the count value with a first threshold value, a line pattern recognition unit for determining the line containing the problem pattern as a problem line, a frame pattern recognition unit for comparing the number of problem lines with a second threshold value, and determining the frame containing the input data as a problem frame, a polarity control signal generating unit for generating vertical and horizontal polarity control signals, and source drive integrated circuits (ICs) for controlling the vertical and horizontal polarities of data voltages supplied to the data lines.

Liquid crystal display and driving method capable of adaptively changing a problem pattern

Discussed is a timing controller. The timing controller includes a receiver, a converter, an aligner, and an EPI transmitter. The receiver receives input RGB data from an external system. The converter converts the input RGB data into input WRGB data. The aligner converts one of W, R, G, and B data, composing the input WRGB data, into 0 to generate conversion WRGB data having bits less than the total number of bits composing the W, R, G, and B data. The EPI transmitter generates WRGB data by adding dummy bits to the conversion WRGB data, and outputs the WRGB data to a source driver IC.

Timing controller, driving method thereof, and flat panel display device using the same

A liquid crystal display includes: a liquid crystal display panel including data lines and gate lines crossing each other; a timing controller that maps data of an input image to polarity patterns of 1-dot inversion and 2-dot inversion, counts the number of positive data and the number of negative data, determines whether any one of the positive data and negative data becomes dominant or not based on a difference between the counted numbers, and selects either one of the 1-dot and 2-dot inversions; a data driving circuit that converts the data of the input image into data voltages to be supplied to the data lines and inverts the polarity of the data voltages by the selected dot inversion; and a gate driving circuit that sequentially supplies gate pulses synchronized with the data voltages to the gate lines.

Liquid crystal display having a function of selecting dot inversion and method of selecting dot inversion thereof

A liquid crystal display includes a liquid crystal panel having liquid crystal cells in a matrix array at crossings of data lines and gate lines, a data drive circuit for providing data signals to the data lines, a gate drive circuit for providing gate signals to the gate lines, and a timing controller for receiving video data and timing signals, for checking a frame frequency of the video data in real-time to detect changes in the frame frequency, and for outputting a gate timing control signal to control the gate driving circuit in response to changes in the frame frequency and a data timing control signal for controlling the data driving circuit, wherein the gate timing control signal controls black data insertion percentage in a frame.

Liquid crystal display and method of driving the same using black data insertion method responsive to changes in frame frequency to prevent flicker

A liquid crystal display and a method of driving the same are disclosed. The liquid crystal display includes a liquid crystal display panel on which data lines and gate lines cross each other, a data driving circuit that converts data of an input image into positive and negative analog data voltages and outputs the data voltages to the data lines, a gate driving circuit sequentially supplying a gate pulse synchronized with the data voltages to the gate lines, and a timing controller that supplies the input image data to the data driving circuit, controls an operation timing of each of the data driving circuit and the gate driving circuit, compares the input image data with a previously stored reference data pattern, and decides whether or not the input image data is the same as the reference data pattern.

Liquid crystal display and method of driving the same

A liquid crystal display and driving method thereof are disclosed. The liquid crystal display according to an embodiment of the invention includes a liquid crystal panel having liquid crystal cells in a matrix array at crossings of data lines and gate lines; a timing controller for receiving a digital video data and synchronous signals, and generating a source output enable signal, a first gate start pulse, a second gate start pulse having a pulse width different from that of the first gate start pulse, a gate shift clock, a first gate output enable signal and a second gate output enable signal; a data driving circuit for providing a data voltage to the data lines in response to a first logic value of the source output enable signal, and any one black gray voltage of a charge share voltage and a precharge voltage to the data lines in response to a second logic value of the source output enable signal; and a gate driving circuit for providing a first gate pulse in synchronization with the data voltage and a second gate pulse in synchronization with the black gray voltage to the gate lines, in response to the first gate start pulse, the second gate start pulse, the gate shift clock, the first gate output enable signal and the second gate output enable signal.

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Daegu, South Korea

Suhyuk Jang