Nvidia Corporation

Suhas Satheesh

Tezaswi Raja

Nishit Harshad Shah

Miguel Rodriguez

Charlie Hwang

Kevin Zhou

Seyed Nima Mozaffari Mojaveri

Kerwin Fu

Jiale Liang

Miloni Mehta

Ram Kumar Ranjith Kumar

Shalimar Rasheed

Gaurav Ajwani

Kevin Ye

Introduced herein is a technique that reliably measures on-die noise of logic in a chip. The introduced technique places a noise measurement system in partitions of the chip that are expected to cause the most noise. The introduced technique utilizes a continuous free-running clock that feeds functional frequency to the noise measurement circuit throughout the noise measurement scan test. This allows the noise measurement circuit to measure the voltage noise of the logic during a shift phase, which was not possible in the conventional noise measurement method. Also, by being able to measure the voltage noise during a shift phase and hence in both phases of the scan test, the introduced technique can perform a more comprehensive noise measurement not only during ATE testing but as part of IST in the field.

Technique for enabling on-die noise measurement during ate testing and IST

Circuitry and a method of determining electrical characteristics of material local to a specific area of a semiconductor wafer. In one embodiment, the method includes sinking or sourcing current through a selected on of a plurality of devices under test (DUTs) on the semiconductor wafer, converting the current sourcing or sinking into a voltage, comparing the converted voltage against a linear voltage ramp, generating an output clock based on the comparison, and measuring a duty cycle of the output clock. In one embodiment, the duty cycle of the output clock is dependent on the current sinking or sourcing through the selected at least one of the plurality of DUTs on the wafer and electrical characteristics of material local to the specific area of the wafer where the selected one of the plurality of DUTs is located are determined based on the duty cycle of the output clock.

Integrated current monitor

Circuitry and a method of determining electrical characteristics of material local to a specific area of a semiconductor wafer is disclosed. In one embodiment, an IC is disclosed that comprises at least one processing subsystem and at least one integrated common current monitor (ICCM) located within the processing subsystem(s). In one embodiment, the ICCM includes current-to-voltage conversion circuitry that converts a current throughput (I) of a selected at least one of the plurality of DUTs to a corresponding voltage for a plurality of regulated drain-to-source voltages (V) across the selected DUT(s). In one embodiment, the ICCM is configured to determine a duty cycle of a voltage that corresponds to the Iand Irepresents electrical characteristics of material local to an area of a semiconductor wafer specific to a location where the ICCM is located.

Integrated current monitor using variable drain-to-source voltages

Circuits that include one or more transmission lines to propagate a signal through a serially-arranged plurality of repeaters, and one or more control circuits to propagate control pulses to the repeaters, wherein a timing and duration of the control pulses is configured to operate the repeaters in current-mode signaling (CMS) mode during a state transition of the signal at the repeaters and to operate the repeaters in voltage-mode signaling (VMS) mode otherwise.

Transient current-mode signaling scheme for on-chip interconnect fabrics

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Santa Clara, CA, United States of America

Suhas Satheesh