Hewlett Packard Enterprise Development LP

Suhas Kumar

John Paul Strachan

Catherine Graves

Thomas Van Vaerenbergh

Amit S Sharma

Martin Foltin

Craig William Warner

Rui Liu

Richard Stanley Williams

Gary A Gibson

Xia Sheng

Kate Norris

Systems and methods are configured to provide a first problem to be solved to a network of memristors. A second problem to be solved can be gradually provided to the network of memristors. Controlled noise can be applied to the network of memristors for at least a portion of time during which the second problem is 'gradually' provided to the network of memristors. A solution to the second problem can be determined.

Quantum-inspired algorithms to solve intractable problems using classical computers

a Systems and methods are provided for matrix tiling to accelerate computing in redundant matrices. The method may include identifying unique submatrices in the matrix; loading values of elements of each unique submatrix into a respective one of the array processors; applying the vector to inputs of each of the array processors; and adding outputs of the array processors according to locations of the unique submatrices in the matrix.

Matrix tiling to accelerate computing in redundant matrices

A method for determining a solution to a constrained optimization problem includes programming a weights matrix of a Hopfield network with a first encoded matrix representation of an initial constrained optimization problem. The method also includes employing the Hopfield network to determine a solution to the initial constrained optimization problem. Additionally, the method includes encoding a plurality of constrained optimization problems associated with a target constrained optimization problem into a plurality of encoded matrix representations each of which are a combination of the first and the second encoded matrix representations. The plurality of encoded matrix representations increases in convergence to the second encoded matrix representation of the target constrained optimization problem sequentially. The method further includes re-programming the weights matrix of the Hopfield network in an iterative manner with the plurality of encoded matrix representations.

Adiabatic annealing scheme and system for edge computing

Systems and methods are provided for implementing a hardware accelerator. The hardware accelerator emulates a neural network, and includes a memristor crossbar array, and a non-linear filter. The memristor crossbar array can be programmed to calculate node values of the neural network. The nodes values can be calculated in accordance with rules to reduce an energy function associated with the neural network. The non-linear filter is coupled to the memristor crossbar array and programmed to harness noise signals that may be present in analog circuitry of the hardware accelerator. The noise signals can be harnessed such that the energy function associated with the neural network converges towards a global minimum and modifies the calculated node values. In some embodiments, the non-liner filter is implemented as a Schmidt trigger comparator.

Systems and methods for harnessing analog noise in efficient optimization problem accelerators

Recurrent neural networks, and methods therefor, are provided with diagonal and programming fluctuation to find energy global minima. The method may include storing the matrix of weights in memory cells of a crossbar array of a recursive neural network prior to operation of the recursive neural network; altering the weights according to a probability distribution; setting the weights to non-zero values in at least one of the memory cells in a diagonal of the memory cells in the crossbar array; and operating the recursive neural network.

Recurrent neural networks with diagonal and programming fluctuation to find energy global minima

Systems are provided for implementing a hardware accelerator. The hardware accelerator emulate a stochastic neural network, and includes a first memristor crossbar array, and a second memristor crossbar array. The first memristor crossbar array can be programmed to calculate node values of the neural network. The nodes values can be calculated in accordance with rules to reduce an energy function associated with the neural network. The second memristor crossbar array is coupled to the first memristor crossbar array and programmed to introduce noise signals into the neural network. The noise signals can be introduced such that the energy function associated with the neural network converges towards a global minimum and modifies the calculated node values.

Systems for introducing memristor random telegraph noise in Hopfield neural networks

Staged neural networks and methods are described herein. In some embodiments, the methods may identify a plurality of second NP hard/complete problems that are similar to the first NP hard/complete problem and identify solutions to the second NP hard/complete problems. The methods may train a deep neural network with the second NP hard/complete problems and the solutions. The methods may provide the first NP hard/complete problem to the trained deep neural network to generate a preliminary solution to the first NP hard/complete problem and provide the preliminary solution to a recursive neural network configured to execute an energy minimization search. The recursive neural network may generate a final solution to the problem based on the preliminary solution.

Staged neural networks for solving NP hard/complete problems

A DPE memristor crossbar array system includes a plurality of partitioned memristor crossbar arrays. Each of the plurality of partitioned memristor crossbar arrays includes a primary memristor crossbar array and a redundant memristor crossbar array. The redundant memristor crossbar array includes values that are mathematically related to values within the primary memristor crossbar array. In addition, the plurality of partitioned memristor crossbar arrays includes a block of shared analog circuits coupled to the plurality of partitioned memristor crossbar arrays. The block of shared analog circuits is to determine a dot product value of voltage values generated by at least one partitioned memristor crossbar array of the plurality of partitioned memristor crossbar arrays.

Self-healing dot-product engine

Systems and methods for providing write process optimization for memristors are described. Write process optimization circuitry manipulates the memristor's write operation, allowing the number of cycles in the write process is reduced. Write process optimization circuitry can include write current integration circuitry that measures an integral of a write current over time. The write optimization circuitry can also include shaping circuitry. The shaping circuitry can shape a write pulse, by determining the pulse's termination, width, and slope. The write pulse is shaped depending upon whether the target memristor device exhibits characteristics of 'maladroit' cells or 'adroit' cells. The pulse shaping circuitry uses the integral and measured write current to terminate the write pulse in a manner that allows the memristor, wherein having maladroit cells and adroit cells, to reach a target state. Thus, utility of memristors is enhanced by realizing an optimized write process with decrease latency and improved efficiency.

Methods and systems for highly optimized memristor write process

A memristor matrix comprising a crossbar array, a multiplexer and a noise control circuit. The noise control circuit may comprise a threshold comparator and a threshold feedback circuit to receive a first threshold and a second threshold and output a threshold signal based, in part, on an output of the threshold comparator.

Tunable memristor noise control

A memristor device includes a first electrode, a second electrode, and a memristor layer disposed between the first electrode and the second electrode. The memristor layer is formed of a metal oxide. The memristor layer includes a plurality of regions that extend between the first electrode and the second electrode. The plurality of regions of the memristor layer are created with different concentrations of oxygen before electrical operation, and, during electrical operation, a voltage-conductance characteristic of the memristor device is controlled based on the different concentrations of oxygen of the plurality of regions. The controlling of the voltage-conductance characteristic includes increasing or decreasing the conductance of the memristor device toward a target conductance at a specific voltage.

Symmetric bipolar switching in memristors for artificial intelligence hardware

A non-Boolean analog system includes a first Mott memristor having a first value of a characteristic, and a second Mott memristor having a second value of the characteristic different than the first value. The system includes a resistance in series with the first and second Mott memristors to form a network having a capacitance and that is operable as a relaxation oscillator. Responsive to electrical excitation, a temperature of the network operating an environment including ambient thermal noise settles at an equilibrium corresponding to a global minimum that is a maximally optimal global solution to a global optimization problem to which the network corresponds.

Non-Boolean analog Mott memristor network

Systems and methods are provided for matrix tiling to accelerate computing in redundant matrices. The method may include identifying unique submatrices in the matrix; loading values of elements of each unique submatrix into a respective one of the array processors; applying the vector to inputs of each of the array processors; and adding outputs of the array processors according to locations of the unique submatrices in the matrix.

An oscillator circuit that includes a voltage source, a resistor, a capacitor, and a nonlinear device. The capacitor and the nonlinear device may be coupled in parallel with one another. The resistor may be coupled in series with the capacitor and the nonlinear device. The voltage source may be coupled in series with the resistor. The voltage source may supply the oscillator circuit with a direct current input signal. The nonlinear device may include an active layer coupled to a first electrode and a second electrode. In response to the direct current input signal, the oscillator circuit may output a spike train including a spike bunch.

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Palo Alto, CA, United States of America

Suhas Kumar