Samsung Electronics Co., Ltd.

Suh Ho Lee

Chul Jin Kim

Jun Ho Huh

Ho Rang Jang

Tomas Scherrer

Ihor Vasyltsov

A semiconductor device includes a processing block which comprises one or more intellectual property (IP) blocks; a scan chain which is electrically connected to the IP blocks, wherein the scan chain block has a scan in (SI) terminal and a scan out (SO) terminal; a pattern generating circuit which generates a data pattern having a plurality of bits and inputs the data pattern to the scan in (SI) terminal of the scan chain; and an analyzing circuit which determines the degree of degradation of each of the IP blocks based on a result pattern output from the scan out (SO) terminal of the scan chain.

Semiconductor device

A data processing system includes a master device and a slave device. The master device includes a first single pad, a first control circuit, a first frame generator configured, and a first processing circuit. The slave device includes a second single pad, a second control circuit, a second frame generator, and a second processing circuit. A clock source is configured to provide a clock signal to the master device and the slave device. The master device communicates with the slave device through a single wire, the single wire being connected between the first single pad and the second single pad, wherein the single wire is bidirectional. A first frame is transmitted from the master device to the slave device, and a second frame is transmitted from the slave device to the master device.

Device including single wire interface and data processing system including the same

A master device communicates with a slave device through an asynchronous serial communications link. The master device includes a single pad configured to communicate a command frame including an address and a data frame including data with the slave device via a single wire; and a processing circuit configured to generate an oversampling clock signal from a clock signal, to perform a synchronization process for selecting one of a plurality of clock phases of the oversampling clock signal, and to perform a sampling process for sampling an each bit value included in the data frame transmitted from the slave device using a clock phase at the same position as the clock phase selected during the synchronization process.

Growing community of inventors

Seongnam-si, South Korea

Suh Ho Lee