Mitsubishi Electric Corporation

Suguru Maki

Kazuya Yamamoto

Miyo Miyashita

Katsumi Miyawaki

Katsuya Kato

Fumimasa Kitabayashi

Hiromitsu Utsumi

Eri Fukuda

Hiroaki Minamide

A transistor () and a matching circuit substrate (-) are provided on a base plate () and connected to each other. A frame () is provided on the base plate () and surrounds the transistor () and the matching circuit substrate (-). The frame () has a smaller linear expansion coefficient than that of the base plate (). A screwing portion () is provided in the frame (). A size of the base plate () is smaller than that of the frame ().

Semiconductor package

An ESD protection circuit is connected in parallel to a MIM capacitor between a first terminal and a second terminal. First Schottky diodes are connected in series to each other and have anodes connected on the first terminal side and cathodes connected on the second terminal side. Second Schottky diodes are connected in series to each other and connected in anti-parallel to the first Schottky diodes. When an RF signal is inputted to neither the first terminal nor the second terminal, the first terminal has a higher DC voltage than that of the second terminal. The number of the first Schottky diodes is greater than the number of the second Schottky diodes. The number of the second Schottky diodes is set such that an amplitude of the RF signal does not attenuate to predetermined amplitude of the RF signal when the RF signal passes through the MIM capacitor.

ESD protection circuit and RF switch

A cascode amplifier includes: first transistors; second transistors cascode-connected with respective first transistors; a first line connected at spaced points to control terminals of the first transistors; a second line connected at spaced points to control terminals of the second transistors; and a capacitance connected between one end of the second line and ground. The second line includes at least two lines connected in parallel with each other.

Cascode amplifier

A power amplifier comprises: an amplifier transistor; a bias circuit supplying bias current to the amplifier transistor; and a collector voltage terminal connected to a collector of the amplifier transistor. The bias circuit includes: a reference voltage terminal into which a reference voltage is input; a power terminal connected to a power source; a transistor having a control terminal connected to the reference voltage terminal, a first terminal connected to the power terminal, and a second terminal that is grounded. The transistor supplies a bias current corresponding to the reference voltage to the amplifier transistor; a variable capacitor connected between the first terminal and a grounding point; and a logic circuit controlling capacitance of the variable capacitor.

Growing community of inventors

Tokyo, Japan

Suguru Maki