Sharp Kabushiki Kaisha Corporation

Kanazawa University

Suguru Kawabata

Kazuya Ishihara

Shinobu Yamazaki

Yoshiji Ohta

Nobuyoshi Awaya

Mitsuru Nakura

Takashi Nakano

Yukio Tamai

Takahiro Takimoto

Kazuhiro Natsuaki

Daisuke Honda

Masayo Uchida

Junya Onishi

Masaaki Uchihashi

Akio Kitagawa

Kazuya Nakayama

The image processing method includes a luminance value information obtaining step of obtaining effective radiance values from a subject, and an image generating step of generating a picture image as a set of unit regions each of which has a luminance value obtained by at least partially removing a regular reflection light component on a surface of the subject from the effective radiance values.

Image processing method and image processing device

An image capturing apparatus that includes a polarizing filter of a slit type in which polarization characteristics are improved is realized. A polarizing unit () of an image capturing apparatus () includes a first polarizer layer () and a second polarizer layer () that hold a dielectric layer () therebetween, and a plurality of slits () that are arranged at regular intervals in a predetermined direction are formed in each of the first polarizer layer () and the second polarizer layer (). A forming material of each of the first polarizer layer () and the second polarizer layer () and a forming material of a wiring layer that controls an operation of a light receiving unit () are selected from Al, Si, Cu, Au, Ag, Pt, W, Ti, Sn, In, Ga, Zn, and a compound or alloy that contains at least one of the foregoing.

Image capturing apparatus

A method of a forming process for a variable resistive element, which is performed in short time comparable to the pulse forming and a writing current in a switching action is the same level as that of the DC forming, is provided. In the forming process, a variable resistive element is changed by voltage pulse application from an initial high resistance state just after produced to a variable resistance state where the switching action is performed. The forming process includes a first step of applying a first pulse having a voltage amplitude lower than a threshold voltage at which the resistance of the variable resistive element is lowered, to between both electrodes of the variable resistive element, and a second step of applying a second pulse having a voltage amplitude having the same polarity as the first pulse and not lower than the threshold voltage, thereto after the first step.

Method of forming process for variable resistive element and non-volatile semiconductor memory device

Provided is a semiconductor memory device that is capable of stably programming with desirable controllability to a desired electric resistance state in a random access programming action and is provided with a variable resistance element. Regardless of a resistance state of a variable resistance element of a memory cell that is a target of a writing action (erasing and programming actions), an erasing voltage pulse for bringing the resistance state of the variable resistance element to an erased state having a lowest resistance value is applied. Thereafter, a programming voltage pulse for bringing the resistance state of the variable resistance element to a desired programmed state is applied to the variable resistance element of the programming action target memory cell. By always applying the programming voltage pulse after having applied the erasing voltage pulse, a plurality of programming voltage pulses being sequentially applied can be avoided.

Semiconductor memory device

A semiconductor memory device includes a memory cell array where a plurality of memory cells are arranged in a matrix, each of the memory cells serially connecting a two-terminal type memory element and a transistor for selection, a first voltage applying circuit that applies a write voltage pulse to a bit line, and a second voltage applying circuit that applies a precharge voltage to a bit line and a common line. In writing the memory cell, after the second voltage applying circuit has both terminals of the memory cell previously precharged to the same voltage, the first voltage applying circuit applies the write voltage pulse to one terminal of the writing target memory cell via the bit line, and while the write voltage pulse is applied, the second voltage applying circuit maintains the application of the precharge voltage to the other terminal of the memory cell via the common line.

Semiconductor memory device and method of driving the same

A nonvolatile semiconductor memory device includes a bit voltage adjusting circuit which, for each bit line, fixes potentials of a selected bit line and a non-selected bit line to a predetermined potential to perform a memory operation and a data voltage adjusting circuit which, for each data line, fixes potentials of a selected data line and a non-selected data line to a predetermined potential to perform a memory operation. Each of the voltage adjusting circuits includes an operational amplifier and a transistor, a voltage required for a memory operation is input to the non-inverted input terminal of the operational amplifier, and the inverted input terminal of the operational amplifier is connected to the bit line or the data line, so that the potential of the bit line or the data line is fixed to a potential of the non-inverted input terminal of the operational amplifier.

Nonvolatile semiconductor memory device

A nonvolatile semiconductor memory device includes a memory cell array for storing user data provided by arranging memory cells each having a variable resistive element having a first electrode, a second electrode, and a variable resistor made of a metal oxide sandwiched between the first and second electrodes. The first and second electrodes are formed of a conductive material forming ohmic junction with the variable resistor and a conductive material forming non-ohmic junction with the variable resistor, respectively. The variable resistor changes between two or more different resistance states by applying a voltage between the electrodes. The resistance state after being changed is maintained in a nonvolatile manner. The variable resistive elements of all memory cells in the memory cell array are set to the highest of the two or more different resistance states in an unused state before the memory cell array is used to store the user data.

Regardless of a resistance state of a variable resistance element of a memory cell that is a target of a writing action (erasing and programming actions), an erasing voltage pulse for bringing the resistance state of the variable resistance element to an erased state having a lowest resistance value is applied. Thereafter, a programming voltage pulse for bringing the resistance state of the variable resistance element to a desired programmed state is applied to the variable resistance element of the programming action target memory cell. By always applying the programming voltage pulse after having applied the erasing voltage pulse, a plurality of programming voltage pulses being sequentially applied can be avoided. Further, the memory cell array is constituted of even-numbers of subbanks, and the application of the erasing voltage pulse in one subbank and the application of the programming voltage pulse in the other subbank are alternately performed.

A nonvolatile semiconductor memory device can carry out a forming process simultaneously on the nonvolatile variable resistive elements of memory cells and make the forming time shorter. The nonvolatile semiconductor memory device has a forming detection circuit provided between the memory cell array and the second selection line (bit line) decoder. The forming detection circuit detects the completion of the forming process for memory cells by measuring the fluctuation in the potential of second selection lines or the current flowing through the second selection lines when applying a voltage pulse for a forming process through the second selection lines simultaneously to the memory cells on which a forming process is to be carried out connected to the same first selection line (word line), and prevents a voltage from being applied to the second selection lines connected to the memory cells where the completion of the forming process is detected.

Growing community of inventors

Osaka, Japan

Suguru Kawabata