Hitachi, Ltd.

Hitachi Tobu Semiconductor

Other

Akita Electronics Co., Ltd.

Hitachi Semiconductor Ltd.

Sugano Toshio

Wakashima Yoshiaki

Watanabe Masayuki

Ono Takashi

Tsukui Seiichiro

Suzuki Shigeru

Tsukui Seiichirou

In the present invention, memory chips are stuck together in stacked fashion by TAB (tape automated bonding), and a multiple memory chip and lead complex like an SOP (small out-line package) is formed of the chips and leads, whereby a memory module of high packaging density can be realized by a flat packaging technique.

Semiconductor memory module having double-sided stacked memory chip layout

Semiconductor memory module having double-sided memory chip layout

Semiconductor memory module having double-sided stacked memory chip

Process for manufacturing a stacked integrated circuit package

In an SIP type module of the type wherein memory ICs are mounted to both surfaces of a substrate, the present invention provides a face package type memory module wherein packaging is made in an inclined direction in place of vertical packaging of the prior art technique and only the memory ICs mounted to the upper surface side of the substrate are deviated to the positions closer to the end portion of the substrate in order to drastically reduce the packaging height.

Semiconductor device

Semiconductor device having particular mounting arrangement

Lead connections means for stacked tab packaged IC chips

In an SIP type module of the type wherein memory ICs are mounted to both surfaces of a substrate, the present invention provides a face package type memory module wherein packaging is made in an inclined direction in place of vertical packaging of the prior art technique and only the memory ICs mounted to the upper surface side of the substrate are deviated to the position closer to the end portion of the substrate in order to drastically reduce the packaging height.

Growing community of inventors

Kokubunji, Japan

Sugano Toshio