Texas Instruments Corporation

Sueann Lim Wei Fen

Anis Fauzi Bin Abdul Aziz

Lee Han Meng@ Eugene Lee

Sarel Bin Ismail

Lee Han Meng@Eugene Lee

Lee Han Meng @ Eugene Lee

A method of making an integrated circuit ('IC') device includes forming a lead frame in a lead frame strip. Only portions of the lead frame are plated with a conductor. A die pad is attached to an unplated portion of said lead frame.

Integrated circuit package fabrication

A leadframe strip for use in making leaded integrated circuit packages includes a plurality of integrally connected leadframes that each have a die attach pad and first and second dam bars located adjacent to opposite first and second sides of the die attach pad, respectively. A plurality of continuous lead structures extend, uninterrupted by other structure, between opposing ones of the dam bars of horizontally adjacent leadframes. The plurality of integrally connected leadframes are arranged in a plurality of vertical columns, wherein die attach pads in one vertical column are vertically offset from die attach pads in adjacent vertical columns.

Leadframe strip with vertically offset die attach pads between adjacent vertical leadframe columns

A method for forming a panel of stacked semiconductor packages includes providing a bottom leadframe (LF) panel including LFs downset each including at least a plurality of terminals. Low side (LS) transistors are attached to the first die attach area. A first clip panel including first clips downset and interconnected are placed on the bottom LF panel. A dielectric interposer is attached on the first clips over the LS transistors. High side (HS) transistors are attached on the interposers. A second clip panel including a plurality of second clips is mated to interconnect to the HS transistors including mating together the second clip panel, first clip panel and bottom LF panel. The LFs can include a second die attach area, and a controller die attached on the second die attach area, and then pads of the controller die wirebonded to the plurality of terminals.

Forming a panel of triple stack semiconductor packages

A semiconductor device has a leadframe with a first () and a parallel second surface, and an assembly pad () bordered by two opposing sides, which include a plurality of through-holes () from the first to the second pad surface. Another pad side includes one or more elongated windows () between the pad surfaces. The second pad surface includes a plurality of grooves. The leadframe further has a plurality of leads () with opposite elongated sides castellated by indents (). Layers () of bondable metals are restricted to localized areas surrounding bond spots. A semiconductor chip () is attached to the pad and wire-bonded () to the bond spots. A package () encapsulates the chip, wires, pad, and lead portions, and secures the leadframe into the package by filling the through-holes, windows, grooves, and indents.

Packaged semiconductor device having leadframe features preventing delamination

A leadframe () for electronic systems comprising a first sub-leadframe () connected by links () to a second sub-leadframe (), the first and second sub-leadframe connected by tiebars () to a frame (); and each link having a neck () suitable for bending the link, the necks arrayed in a line () operable as the axis for bending the second sub-leadframe towards the first sub-leadframe with the necks operable as rotation pivots.

Flippable leadframe for packaged electronic system having vertically stacked chips and components

A method for forming a stacked semiconductor package includes providing a bottom leadframe (LF) panel including LFs downset each including at least a plurality of terminals. Low side (LS) transistors are attached to the first die attach area. A first clip panel including first clips downset and interconnected are placed on the bottom LF panel. A dielectric interposer is attached on the first clips over the LS transistors. High side (HS) transistors are attached on the interposers. A second clip panel including a plurality of second clips is mated to interconnect to the HS transistors including mating together the second clip panel, first clip panel and bottom LF panel. The LFs can include a second die attach area, and a controller die attached on the second die attach area, and then pads of the controller die wirebonded to the plurality of terminals.

Triple stack semiconductor package

A lead frame device may include an integral die pad member, two separate finger members, a central body portion, each of the finger members have a top and a bottom surface connected by a peripheral edge surface. The lead frame also has a first ear portion, and a second ear portion, each has an ear top surface and an ear bottom surface coplanar with the top surface and bottom surface of the central body portion. The lead frame also has a first longitudinally extending groove and second longitudinally extending groove separate the first ear portion and the second ear portion from the central portion. The first ear portion and the second ear portion each have an abutment surface.

Lead frame with abutment surface

An integrated circuit ('IC') device and method of making it. The IC device may include a conductive lead frame that has a die pad with a relatively larger central body portion and at least one relatively smaller peripheral portion in electrical continuity with the central body portion. The peripheral portion(s) project laterally outwardly from the central body portion of the die pad. Lateral displacement of a portion(s) of an encapsulation layer overlying the peripheral portion(s) is resisted by abutting surfaces on the peripheral portion(s) and the encapsulation layer.

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Sueann Lim Wei Fen