International Business Machines Corporation

Sue Ellen Strang

Donald L Jordan

Steven H Voldman

David Goren

David S Collins

Raminderpal Singh

Rachel Gordin

Kurt Alan Tallman

Youri V Tretiakov

Carl E Dickey

Donald Lee Jordan

Ronald Keith Case

A method for determining the layout of an interconnect line is provided including: providing a required width for the interconnect line; determining a layout of the interconnect line including slotting the interconnect line to provide two or more fingers extending along the interconnect line with an elongate slot separating adjacent fingers; and determining a number of elongate apertures to be arranged across the width of the interconnect line by comparing the required width with a maximal width for a solid metal feature, and a minimal elongate aperture width. The two or more fingers and elongate slot may be of constant width and equally spaced across the interconnect line width. The method may include selecting the number of fingers and the width of the slots to optimize the layout for a given layer technology.

Layout determining for wide wire on-chip interconnect lines

A computerized method and system for designing, verification and checking of the electrostatic discharge (ESD) protection circuits and their implementation in a integrated computer chip design where the computer chip comprises of electronic circuits designed in a parameterized cell design system, pads, interconnects and the ESD system uses a hierarchical system of parameterized cells (p-cells) which are constructed into higher level ESD networks. Lowest order p-cells pass user defined parameters to higher order p-cells to form an ESD protection circuit meeting design criteria. Ones of the p-cells are 'grow-able' such that they can form repetition groups of the underlying p-cell element to accommodate the design parameters. Layout and circuit schematics are auto-generated with the user varying the number of elements in the circuit by adjusting the input parameters. The circuit topology automation allows for the customer to auto generate new ESD circuits and ESD power clamps without additional design work.

ESD design, verification and checking system and method of use

A method for designing integrated circuits comprising: partitioning interconnects of an integrated circuit design based on partition criteria to create sets of interconnect partitions; selecting at least one analysis method from a set of analysis methods to be performed on interconnects of each set of interconnect partitions; and performing each selected analysis method on interconnects of each corresponding interconnect partition.

Method and system for integrated circuit design

A system and method is provided for that allows the introduction of small sections of idealized conductive elements to be placed along a transmission line. The output is a partitioned transmission line whose segments between the idealized conductive elements are analyzed via circuit simulators as a distributed parasitic network, as opposed to the widely used lumped parasitic elements approach for the entire line. The distributed parasitic network system and method provides circuit designers with a parasitic extraction tool which allows the designer to define a transmission line segment for analysis, and create sub-networks of parasitic elements across the transmission line. These elements can then be passed to existing vendor circuit simulators for parasitic analysis, the result of which are more accurate than that derived using existing extraction tools whose output is limited to only a lumped parasitic parameter along the line.

Practical distributed transmission line analysis

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Burlington, VT, United States of America

Sue Ellen Strang