Texas Instruments Corporation

Sue E Crank

Peijun Chen

Duofeng Yue

Thomas Dyer Bonifield

Amitabh Jain

Homi C Mogul

Cecil J Davis

Rhett B Jucha

Jiong-Ping Lu

Duane E Carter

Amitava Chatterjee

Kaiping Liu

Deborah J Riley

Song Zhao

Lance Stanford Robertson

John I Jones

Trace Quentin Hurd

Donald S Miles

Shawn T Walsh

James B Friedmann

Byron T Ahlburn

Shirin Siddiqui

John E Campbell

Thomas M Parrill

Der'E Jan

Joshua J Robbins

Jie-Jie Xu

The invention provides a semiconductor device, a method of manufacture therefore and a method for manufacturing an integrated circuit including the same. The semiconductor device, among other elements, may include a gate structure located over a substrate, the gate structure including a gate dielectric layer and gate electrode layer. The semiconductor device may further include source/drain regions located in/over the substrate and adjacent the gate structure, and a nickel alloy silicide located in the source/drain regions, the nickel alloy silicide having an amount of indium located therein.

Nickel alloy silicide including indium and a method of manufacture therefor

The present invention provides a semiconductor device, a method of manufacture therefore and a method for manufacturing an integrated circuit including the same. The semiconductor device, among other elements, may include a substrate (), as well as a nickel silicide region () located over the substrate (), the nickel silicide region () having an amount of indium located therein.

Nickel silicide including indium and a method of manufacture therefor

The present invention provides a method of manufacturing a metal silicide electrode () for a semiconductor device (). The method comprises implanting small atoms into an nMOS semiconductor substrate () to a depth () no greater than about 30 nanometers into the nMOS semiconductor substrate. The method further comprises depositing a transition metal layer () over the nMOS semiconductor substrate. The transition metal layer and the nMOS semiconductor substrate are reacted to form the metal silicide electrode. Other aspects of the present invention include a method of manufacturing an integrated circuit ().

Metal silicide induced lateral excessive encroachment reduction by silicon &#x3c;110&#x3e; channel stuffing

A method of preparing a die comprises treating exposed silicon to form an oxide prior to silicide formation; and depositing metal on the oxide. The metal may comprise titanium, cobalt, nickel, platinum, palladium, tungsten, molybdenum, or combinations thereof on the oxide. The oxide may be less than or equal to about 15 angstroms thick. In various embodiments, treating exposed silicon to form an oxide comprises forming a non-thermal oxide. Treating exposed silicon to form an oxide may also comprise treating the exposed silicon with an oxidizing plasma; alternatively, treating exposed silicon to form an oxide may comprise forming a chemical oxide. In certain other embodiments, treating exposed silicon to form an oxide comprises treating exposed silicon with a solution comprising ammonium hydroxide, hydrogen peroxide, and water; hydrochloric acid, hydrogen peroxide, and water; hydrogen peroxide; ozone; ozonated deionized water; or combinations thereof.

Treatment of silicon prior to nickel silicide formation

A method for forming metal silicide regions in source and drain regions () is described. Prior to the thermal annealing of the source and drain regions (), germanium is implanted into a semiconductor substrate adjacent to sidewall structures () formed adjacent gate structures (). The position of the implanted germanium species in the semiconductor substrate will overlap the source and drain regions (). Following thermal annealing of the source and drain regions (), the implanted germanium prevents the formation of metal silicide spikes.

Silicide method for CMOS integrated circuits

A method is given for removing excess oxide from active areas after shallow trench isolation, without the use of chemical-mechanical polishing. A nitride mask protects active areas during the etch of isolation trenches. The trenches are filled with oxide, using high density plasma deposition, which simultaneously etches, providing a sloping contour around the isolation trenches. A further layer of nitride is used to provide a cap over the trench which seals to the underlying layer of nitride. The cap layer of nitride receives a patterned etch to remove the cap only over the active areas. This allows a selective etch to remove the excess oxide, which can be followed by a selective etch to remove the nitride layers.

Method for trench isolation of semiconductor devices

An improved metallized structure (10) is formed from a copper seed layer (46) and a copper structure (48). Semiconductor devices to be connected (16-18) are covered by a conductive barrier layer (20). An oxide layer (28) is then deposited over the barrier layer (20) and patterned using standard photolithographic techniques and an anisotropic plasma etch. Vertical sidewalls (36-38) are formed by the etch and an HF deglaze. A seed layer (44-46) is then sputtered onto a photoresist layer (30) and the exposed barrier layer (20). After stripping the photoresist (30) and the seed layer (44) thereon, the copper structure (48) is electroplated over the remaining seed layer (46). The structure (48) thus formed has approximately vertical sidewalls (24-26) for improved contact with subsequent layers.

Integrated circuit copper metallization process using a lift-off seed

A thin film etching process, wherein the rate of deposition of a robust sidewall passivant is controlled so that passivants can be continually deposited on the sidewalls of the resist pattern to change the geometry of the resist pattern during the processing step. That is, the existing pattern is modified as if a sidewall filament has been deposited on it, which can be advantageous for many purposes, without the added process complexity required by a sidewall filament process.

Selective etching of tungsten by remote and in situ plasma generation

Tungsten is rapidly and anisotropically etched under plasma bombardment conditions by using a feed gas mixture which includes a fluorine source (such as SF.sub.6) plus a bromine source (such as HBr), plus a hydrocarbon source (e.g., an alkyl, such as methane).

Method for etching tungsten

A fluorine based metal etch chemistry, wherein an admixture of etch products (or species which are closely related to etch products) is added during the post etch stage, i.e. during the stage when the pattern has partially cleared by overetch is not yet completed, to maintain the balance of chemistries which provides selectivity and anisotropy. In a tungsten etch, WF.sub.6 is usefully added during the post etch period to provide this loading.

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Coppell, TX, United States of America

Sue E Crank