Cadence Design Systems, Inc.

Sudipta Sarkar

Steven Elliott Mikes

Mehran Mohammadi Izad

Dimitrios Loizos

Manohar Bhavsar Nagaraju

Paul Lee

Embodiments included herein are directed towards a fractional feedback divider circuit and associated method. The circuit may include a programmable feedback divider including a plurality of flip-flops arranged in series. The programmable feedback divider may be configured to receive an input clock signal and a reset signal comprising at least one pulse and to generate a divided clock. The circuit may include reset logic configured to receive an input from the programmable feedback divider and to generate a reset signal. The circuit may include a first D flip-flop configured to receive the reset signal and to generate an output and a second D flip-flop configured to receive the output from the first D flip-flop and to generate a second output. The circuit may further include a multiplexer configured to receive the second output and to generate an output clock signal.

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San Jose, CA, United States of America

Sudipta Sarkar