Xilinx, Inc.

Cswitch Corporation

Agate Logic, Inc.

Csitch Corporation

Sudip K Nag

Hare Krishna Verma

Jason Helge Anderson

Anirban Rahut

Srinivasan Dasasathyan

Guenter Stenz

Rajeev Jayaraman

James L Saunders

Ravi S Sunkavalli

Kamal Chaudhary

Krishnan Anandh

Jason H Anderson

Sandor S Kalman

Madabhushi V R Chari

Elliott Delaye

Vinay Verma

Bo Hu

Chandra Mulpuri

Ashok Vittal

Conrad Kong

Sridhar Krishnamurthy

Nagaraj Narasimh Savithri

Sankaranarayanan Srinivasan

Qiang Wang

Rajat Aggarwal

Richard Yachyang Sun

Sanjeev Kwatra

Vishal Suthar

Hasan Arslan

Atul Srinivasan

Vinod K Nakkala

Jennifer Zhuang

Guenther Stenz

Pavanish Nirula

Gi-Joon Nam

Determining delays of paths in a circuit design includes determining whether or not each path of the plurality of paths matches a path definition of a plurality of path definitions in a path database. For each path that matches a path definition, a first path delay value associated with the matching path definition is read from the path database and associated with the matching path of the circuit design. For each path that does not match any of the path definitions, respective element delay values of elements of the path are read from an element database. A second path delay value of the non-matching path is computed as a function of the respective element delay values, and the second path delay value is associated with the path. The first and second path delay values are output along with information indicating the associated paths.

Determination of path delays in circuit designs

A method of implementing a circuit design within a programmable integrated circuit (IC) can include identifying an implementation directive embedded within a register transfer level (RTL) description of the circuit design and determining components of a sub-circuit of the circuit design, wherein the sub-circuit is specified by a portion of the RTL description associated with the implementation directive. The sub-circuit can be placed for the programmable IC and routed for the programmable IC according to the implementation directive. A programmatic description of the sub-circuit specifying placement and routing information can be output.

Implementing sub-circuits with predictable behavior within a circuit design

A programmable logic structure is disclosed employing input logic routing cell (ILRC) multiplexers and output logic routing cell (OLRC) multiplexers for making local connections between dedicated logic cells. In a simple programmable logic structure, a dedicated logic cell (DLC) is implemented in a programmable logic structure comprising multiple ILRC multiplexers for port A and multiple OLRC multiplexers for port B. In a multi-level programmable logic structure, multiple columns of dedicated logic cells is designed with columns of dedicated local cells adjacent to each other where each DLC column is used to implement a particular logic function. In a first embodiment, local connections can be made between dedicated logic cells, e.g. an OLRC in a first DLC at level L making local point-to-point connections to an ILRC in a second DLC at level L+1. In a second embodiment, local connections can be made from any other dedicated logic cells, whether positioned horizontally or vertically relative to a relative point or multiplexer, and from any offset from a current logic and routing cell (LRC). In a third embodiment, local connections can be made by stitching a first OLRC to a second OLRC (for connecting to an ILRC), which allows lines from other columns or levels of DLC to reach an ILRC for a fast local interconnect.

Programmable logic cells with local connections

Method and apparatus for facilitating signal routing within a programmable logic device having routing resources is described. In an example, the routing resources are formed into groups where, for each of the groups, the routing resources are of a same type. Pairs of the groups are related by an association of at least one routing resource in one group of a pair of groups capable of being electrically connected to at least one other routing resource in another group of the pair of groups.

Method and apparatus for facilitating signal routing within a programmable logic device

Logic design apparatus and method provides serial multiplexer chains in a programmable logic fabric, each element in the chain either selects output of block, or passes output from earlier element of the chain. Select line is a decoder structure or output from configurable function generator that is configured at power-on to create correct selection. Using such structure, larger multiplexer, including priority multiplexers, tristate buses or larger look-up tables (LUTs) can be created. These novel structures can implement priority, non-priority or tristate multiplexers.

Versatile multiplexer-structures in programmable logic using serial chaining and novel selection schemes

Method and apparatus are described for a placer system for placing design objects onto an arrayed architecture, such as a programmable logic device including an FPGA. More particularly, a placer interface is described for communicating with a placer core. The placer interface receives information from external entities, and unifies and generalizes this information for the placer core. The external entities comprise different representations of architecture, design, device, constraints and algorithm-dictated placer-movable objects.

Unified placer infrastructure

A method () of placing local clock nets in a circuit design can include identifying the local clock nets for the circuit design and selecting components corresponding to each local clock net (), and assigning initial locations to each component of the local clock nets (). The method further can include generating at least one cost function () to evaluate () different placements of components of the local clock nets. The components () of the local clock nets () can be annealed () using one or more of the cost functions to assign locations to each component of the local clock nets.

Automated local clock placement for FPGA designs

Method and apparatus for forming timing parameters for a circuit design having a predefined routing topology within an integrated circuit is described. Sets of timing attributes are determined for the routing topology, each set of timing attributes being associated with one of a plurality of locations within the integrated circuit in which the circuit design may be placed. Timing parameters are formed in response to the sets of timing attributes. The timing parameters are then associated with the routing topology.

Method and apparatus for timing characterization of integrated circuit designs

Application of network flow techniques to constrained optimization problems is disclosed. The present of constrains may lead to infeasible solutions. The infeasible solutions can be removed by an iterative process of changing the structure of the network and/or the associated parameters. Specific applications of the invention to the placement of tristate buffers and clocks in integrated circuits are disclosed.

Method for application of network flow techniques under constraints

Within a computer automated tool, a method of physical circuit design can include assigning initial locations to components in the circuit design and determining an initial routing of connections between components in the circuit design using an overlap mode. The method also can include determining timing critical connections and selectively relocating components with at least one timing critical connection prior to performing a detailed routing of the circuit design.

Using router feedback for placement improvements for logic design

Method and apparatus for post-placement optimization of resources for connections is described. To optimize resource placement, search windows are generated responsive to driver and load components, as well as to a connection between the driver and load components. Adding in a straight-line path search window may be used as an alternative where a bypassed resource is to be relocated. Using connection-based optimization in combination with driver- and resource-based optimization results in improved optimization with negligible impact on runtime.

Relocation of components for post-placement optimization

Within a computer automated tool, a method () of estimating an upper-bound of an operational frequency of at least a portion of a placed circuit design can include identifying () a clock source within the placed circuit design, wherein the clock source is associated with a clock domain, and determining () an initial routing of the clock domain. The method also can include determining () a minimum path slack corresponding to each connection of the clock domain. Connections of the clock domain which have a lowest minimum path slack can be marked (). One or more marked connections which are not routed in delay mode can be identified and routed in delay mode () allowing sharing of routing resources by different nets.

Upper-bound calculation for placed circuit design performance

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San Jose, CA, United States of America

Sudip K Nag