Nvidia Corporation

Sudhir Shrikantha Kudva

Nikola Nedovic

John M Wilson

Carl Thomas Gray

John Wood Poulton

William James Dally

Stephen G Tell

Thomas Hastings Greer

Sanquan Song

Mahmut Ersin Sinangil

Ahmed Abou-Alfotouh

Yan He

PUF cells utilizing a dual-interlocking scheme demonstrating improved noise immunity and stability across different V/T conditions and different uses over time in noisy environments. The PUF cell may be advantageously utilized in conjunction with error detection techniques that screen out unstable cells. A set of such PUF cells utilized to generate a device-specific bit pattern, for example a master key.

Physically unclonable cell using dual-interlocking and error correction techniques

Systems and methods are disclosed related to low-power dynamic offset calibration of an error amplifier. An analog linear voltage regulator circuit tracks changes between a reference voltage and a regulated voltage to keep the regulated voltage as close as possible to the reference voltage. The analog linear voltage regulator includes an error amplifier that measures the error between the reference and regulated voltages and feedback circuitry. The error amplifier and feedback circuitry should be calibrated to correct for any offset within the circuits. The described offset calibration technique not only compensates for the offset in the error amplifier but also cancels any mismatch in the feedback network. During operation, conditions such as temperature and supply voltage may vary causing the offset to change. The technique is low power and dynamically cancels the offset even when the linear regulator is operating to supply the desired voltage.

Low-power dynamic offset calibration of an error amplifier

A circuit includes a set of multiple bit generating cells. One or more adjustable characterization circuits are coupled to inputs to the bit generating cells to affect the outputs of the bit generating cells. Based on the effect of the characterization circuit(s) on the outputs of the bit generating cells, a subset less than all of the bit generating cells is selected.

Detection and mitigation of unstable cells in unclonable cell array

Bit generating cells are subjected to processes that accelerate aging-related characteristics before they are configured for use in the field (enrolled). Aging improves the reliability of the cells by shifting device characteristic in a direction that improves the cell behavior with respect not only to aging but also environment variations. Outputs of the cells are read, and the cells are reconfigured with a bias to output an opposite value, and then aged for enrollment.

Stability of bit generating cells through aging

Various implementations of a current flattening circuit are disclosed, including those utilizing a feedback current regulator, a feedforward current regulator, and a constant current source.

Current flattening circuit for protection against power side channel attacks

This disclosure relates to current flattening circuits for an electrical load. The current flattening circuits incorporate randomize various parameters to add noise onto the supply current. This added noise may act to reduce the signal to noise ratio in the supply current, increasing the difficulty of identifying a computational artifact signal from power rail noise.

Techniques to improve current regulator capability to protect the secured circuit from power side channel attack

A circuit includes a set of multiple bit generating cells. One or more adjustable current sources is coupled to introduce perturbations into outputs of the bit generating cells. Based on the perturbations, the outputs of a subset less than all of the bit generating cells are selected, and applied as a control.

High-resolution switched digital regulators are disclosed having fast cross corner and variable temperature response, with constrained ripple. The strength of the power transistors utilized by the regulator are adjusted to control the current delivered to the load. The regulators utilize a slow control loop in parallel with a primary fast switching loop. The slow loop uses the switching signal of the primary loop to estimate the load current and set the power transistor size accordingly.

Switched low-dropout voltage regulator

A circuit, method, and system are disclosed for sampling a signal. The system includes a sampler circuit configured to sample input signals when a clock signal is at a first voltage level to produce sampled signals, a detection circuit that is coupled to the sampler circuit, and a feedback circuit that receives an output signal and generates the clock signal. The detection circuit pre-charges the sampled signals when the clock signal is at a second voltage level and, using threshold adjusted inverters, detects voltage levels of each sampled signal to produce detected voltage levels, where a threshold voltage of the threshold adjusted inverters is entirely outside of a transition voltage range of the sampler circuit. In response to one of the detected voltage levels transitioning from the second level to the first level, the detection circuit transitions the output signal from the first voltage level to the second voltage level.

Self-clocking sampler with reduced metastability

A circuit, method, and system are disclosed for sampling a signal. The system includes a sampler circuit configured to sample input signals when a clock signal is at a first level to produce sampled signals, a detection circuit that is coupled to the sampler circuit, and a feedback circuit that receives an output signal and generates the clock signal. The detection circuit pre-charges the sampled signals when the clock signal is at a second level and, using threshold adjusted inverters, detects voltage levels of each sampled signal to produce detected voltage level signals, where a threshold voltage of the threshold adjusted inverters is entirely outside of a transition voltage range of the sampler circuit. In response to one of the detected voltage level signals transitioning from the second level to the first level, the detection circuit transitions the output signal from the first level to the second level.

A DC-DC converter circuit includes a switched tank converter configured to output a switching waveform. The DC-DC converter circuit further includes a transformer coupled to the switched tank converter to receive the switching waveform output by the switched tank converter across a primary winding of the transformer.

Switched tank-transformer based high step-down ratio DC-DC converter

A system and method are provided for controlling a modified buck converter circuit. A pull-up switching mechanism that is coupled to an upstream terminal of an inductor within a modified buck converter circuit is enabled. A load current at the output of the modified buck regulator circuit is measured. A capacitor current associated with a capacitor that is coupled to a downstream terminal of the inductor is continuously sensed and the pull-up switching mechanism is disabled when the capacitor current is greater than a sum of the load current and an enabling current value.

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Dublin, CA, United States of America

Sudhir Shrikantha Kudva