Texas Instruments Corporation

Sudhir Nagaraj

Rakesh Raja

Sooping Saw

Anuj Jain

Michael Edwin Butenhoff

Paul Vulpoiu

Wen Pin Lin

Wenchao Qu

Seung Bae Lee

David H Elwart, Ii

A method for electrically producing a stalled state in a stepper motor having a first coil and a second coil is provided. The method includes driving a first sinusoidal current through the first coil, and driving a second sinusoidal current through the second coil, wherein the first and second sinusoidal currents are in phase.

Stepper motor

In one embodiment, a method includes detecting, by a stall detection sensor in a driver coupled to a stepper motor, a first set of time-off periods in a rising commutation phase of motor current during current regulation. The stall detection sensor further detects a second set of time-off periods in a falling commutation phase of motor current during current regulation. Next, the stall detection sensor compares the first set of time-off periods with the second set of time-off periods and determines whether the stepper motor is stalled based on the comparison of the first set of time-off periods with the second set of time-off periods.

Stall detection in stepper motors using differential back-EMF between rising and falling commutation phase of motor current

An analog signal-to-pulse width modulation (PWM) converter includes a ramp generator generating a ramp signal and a comparator circuit comparing the ramp signal to a first voltage, a second voltage, and to an analog input signal. A duty cycle calculation circuit generates a first control signal to the ramp generator to generate the ramp signal. Based on signals from the comparator circuit, the duty cycle calculation circuit calculates the ratio of the time it takes for the ramp signal to exceed the analog input signal from when the ramp signal exceeds the first voltage to the time it takes for the ramp signal to exceed the second voltage from when the ramp signal exceeds the first voltage. A PWM signal generator generates a PWM output signal based on the ratio calculated by the duty cycle calculation circuit.

Pulse width modulation technique with time-ratio duty cycle computation

An analog signal-to-pulse width modulation (PWM) converter includes a ramp generator generating a ramp signal and a comparator circuit comparing the ramp signal to a first voltage, a second voltage, and an analog input signal. A duty cycle calculation circuit generates a first control signal to the ramp generator to generate the ramp signal. Based on signals from the comparator circuit, the duty cycle calculation circuit calculates the ratio of the time it takes for the ramp signal to exceed the analog input signal from when the ramp signal exceeds the first voltage to the time it takes for the ramp signal to exceed the second voltage from when the ramp signal exceeds the first voltage. A PWM signal generator generates a PWM output signal based on the ratio calculated by the duty cycle calculation circuit.

Reducing noise for an amplifier-based system circuit that comprises a first differential input pair and a second differential input pair, a first input stage circuit connected to the first differential input pair, wherein the first input stage is configured with a first transconductance value, a second input stage circuit connected to the second differential input pair, wherein the second input stage is configured with a second transconductance value that is less than the first transconductance value, a transimpedance circuit coupled to the first input stage circuit and the second input stage circuit, and a feedback loop circuit coupled to the transimpedance circuit and to the second differential input pair, wherein the feedback loop circuit is not connected to the first differential input pair.

Transconductance shifted differential difference amplifier

A system comprises a buffer circuit coupled to a comparator, and an adaptive threshold control circuit coupled to a timer and comparator. Buffer circuit receives a first voltage across a control terminal and a first current terminal of a transistor and a second voltage across a second current terminal and the first current terminal of the transistor. Comparator compares first voltage to a first threshold, generating a first trigger signal when it crosses first threshold, and compares second voltage to a second threshold, generating a second trigger signal when it crosses second threshold. Timer determines length of time between trigger signals. Adaptive threshold control circuit generates a first control signal for first trigger signal, and a second control signal for second trigger signal, and provides a control signal to comparator indicative of whether length of time is greater than or less than user-programmed value, causing comparator to adjust first threshold.

Adaptive threshold control system for detecting and adjusting the duration of regions of operation during transistor turn on and turn off

A motor controller that includes a processing device and a drive circuit. The drive circuit may include a plurality of switches, a motor winding, and a current sensor coupled together in an H-bridge configuration. The processing device is configured to cause a drive current to drive through the motor winding for a minimum amount of time. The processing device is also configured to compare the current through the current sensor to a threshold value at the minimum amount of time. The processing device is also configured to, based on the current being at or above the threshold value at the minimum amount of time, stop the drive current for an off period of time and cause a first decay of the current for a first percentage of the off period of time and a first slow decay for a second percentage of the off period of time.

Current regulation in motors

A system and method for a decay lock loop for time varying current regulation in electric motors determines if a predetermined electrical current regulation level for an electric motor has been obtained within a tuning control time window. A coarse control loop increases or decreases a fast current decay, in response to a determination that the predetermined electrical current regulation level has not been obtained within the tuning control time window, until the predetermined electrical current regulation level falls within the tuning control time window. A fine control loop increments or decrements an amount of fast current decay during a total decay time, in response to a determination that the predetermined electrical current regulation level has been obtained within the tuning control time window, until a predetermined timing of the predetermined electrical current regulation level has been obtained.

Decay lock loop for time varying current regulation in electric motors

Input codes are sequenced at a lower-resolution linear DAC and the output is converted to a linear current waveform. A first of two interconnected analog current multipliers multiplies the linear current by itself and by the inverse of a first constant current source to create a quadratic current output. A second current multiplier multiplies the quadratic output current by the linear current and by the inverse of a second constant current source to generate a cubic current output. The quadratic and cubic currents are subtracted from the linear current to generate an approximation of the first 180 degrees of a sine wave current. Alternate (pi to 2*pi) positive-going one-half sine waves may be polarity reversed to create a complete positive-going and negative-going sine-shaped electrical current of higher resolution than is available from a sine DAC of resolution equivalent to that of the lower-resolution linear DAC.

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Dallas, TX, United States of America

Sudhir Nagaraj