Texas Instruments Corporation

Sudheer Prasad

Md Abidur Rahman

Ankur Chauhan

Subrato Roy

Sandeep Kesrimal Oswal

Xiaoju Wu

Anindya Saha

Bhupendra Sharma

Anmol Sharma

Ravindra Karnad

Arthur Miller

Vivek Gorakhnath Pawar

Baireddy Vijayavardhan

Krishnan Ramabhadran

Suresh R Puthucode

Rajesh Keloth

Ram A Jonnavithula

Subhash Madireddy

In one example an amplifier includes a bias circuit, an open-loop gain stage including a first PMOS having a gate coupled to a first node, a source coupled to a second node, a drain coupled to a third node, and a bulk coupled to the bias circuit, a second PMOS having a gate coupled to a ground node, a source coupled to the second node, a drain coupled to a fourth node, and a bulk coupled to the bias circuit, a first NMOS having a drain and a gate coupled to the third node and a source coupled to a fifth node, a second NMOS having a drain coupled to the fourth node, a gate coupled to the third node, and a source coupled to the fifth node, an adjustable resistor coupleable between the third and fourth nodes, and a buffer stage coupled to the open-loop gain stage.

Biased amplifier

A system includes: 1) a buffer circuit; 2) circuitry coupled to an input of the buffer circuit; 3) a load coupled to an output of the buffer circuit; and 4) a clamp circuit coupled between an input of the buffer circuit and the output of the buffer circuit. The clamp circuit includes: 1) a bipolar junction transistor (BJT); 2) a first resistor with a first end coupled to a base terminal of the BJT and with a second end coupled to a collector terminal of the BJT; and 3) a second resistor with a first end coupled to the collector terminal of the BJT and with a second end coupled to the input of the buffer circuit. The second resistor is between an output of the circuitry and the input of the buffer circuit.

Slow clamp circuit for bipolar junction transistor (BJT) buffers

An interface device includes an NPN structure along a horizontal surface of a p-doped substrate. The NPN structure has a first n-doped region coupled to an output terminal, a p-doped region surrounding the first n-doped region and coupled to the output terminal, and a second n-doped region separated from the first n-doped region by the p-doped region. The interface device also includes a PNP structure along a vertical depth of the p-doped substrate. The PNP structure includes the p-doped region, an n-doped layer under the p-doped region, and the p-doped substrate. Advantageously, the interface device can withstand high voltage swing (both positive and negative), prevent sinking and sourcing large load current, and avoid entering into a low resistance mode during power down operations.

Output driver with power down protection

An apparatus includes: a first power transistor having a first current conduction path coupled between an input for receiving a supply voltage and a node and a first gate terminal coupled to a first gate control signal; a second power transistor having a second current conduction path coupled between the node and an output terminal for supplying a load current to a load; and a second gate terminal coupled to a second gate control signal; and a current sense transistor having a third gate terminal coupled to the first gate control signal, and outputting a sense current. The apparatus further includes: a differential amplifier having an output signal, and a feedback transistor having a gate terminal coupled to the output signal of the differential amplifier; and a resistor coupled between a monitor node and ground.

Current sensing and control for a transistor power switch

A detection circuit includes a first transistor coupled to a gate of a high power transistor, a second transistor whose source is coupled to a drain of the first transistor, a first voltage divider coupled to a source of the first transistor, and a second voltage divider coupled to the source of the second transistor. The first transistor is configured to generate a first transistor output voltage representative of a gate voltage of the high power transistor shifted based on a first gate-to-source voltage of the first transistor. The second transistor is configured to generate a second gate-to-source voltage substantially equal to the first gate-to-source voltage. The first divider is configured to divide the first transistor output voltage by a first factor. The second divider is configured to divide the second gate-to-source voltage by a second factor correlated with the first factor.

Correcting high voltage source follower level shift

One example includes a hot-swap control system. The system includes a sense resistor network provides a sense voltage in response to an output current. The system also includes a sense control circuit includes a chopper amplifier system arranged in a servo feedback arrangement to generate a monitoring voltage having an amplitude that is associated with the output current based on the sense voltage. A notch filter chopping stage filters out signal ripple in the chopper amplifier system across a unity-gain bandwidth of the chopper amplifier system, and a capacitive compensation network provides stability-compensation of the chopper amplifier system across the unity-gain bandwidth. A transconductance amplifier configured to compare the monitoring voltage with a predetermined reference voltage to generate a control voltage. The system further includes a power transistor configured to conduct the output current to an output based on the control voltage.

Hot-swap current-sensing system

A circuit for controlling temperature of a semiconductor chip includes a first heating element that is built into the semiconductor chip. The first heating element generates heat to increase the temperature of the semiconductor chip. The chip also includes a temperature controller that is coupled to the first heating element and built into the semiconductor chip. The temperature controller controls the temperature to enable testing of the semiconductor chip at a desired temperature.

Circuit for controlling temperature and enabling testing of a semiconductor chip

A characteristic is measured on multiple portions of an integrated circuit, and the supply voltage adjusted based on the measurements. In an embodiment, the characteristic corresponds to propagation delay which indicates whether the integrated circuit is implemented with a strong, weak or nominal process corner. In general, the supply voltage can be increased in the case of a weak process corner and decreased in the case of a strong process corner.

Providing optimal supply voltage to integrated circuits

Ensuring sufficient bias current is provided to a portion of a circuit containing low voltage transistors operating with a high supply voltage. Such a sufficient bias current may be ensured by generating a primary bias current from a low supply voltage and a backup bias current from a high supply voltage, and providing the backup bias current as the bias current if the primary bias current is not present. The primary bias current may be provided as the bias current when the low supply voltage is available. Thus, the backup bias current is provided as bias current in case of undesirable supply sequencing.

Avoiding excessive cross-terminal voltages of low voltage transistors due to undesirable supply-sequencing in environments with higher supply voltages

An aspect of the present invention provides multiple switches in a transceiver, which enable pins provided for transmission and reception to be connected to either a transmit port or a receive port, as desired during operation. As a result, the transceiver can be auto-configured to connect the specific pin, on which signals are being received, to the receive port. Similarly, the transceiver can be auto-configured to connect the specific pin, on which the signals need to be transmitted, to the transmit port. Various design considerations in providing such switches are also described.

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Bengaluru, India

Sudheer Prasad