Cypress Semiconductor Corporation

Sudhaker Reddy Anumula

Jeffery Scott Hunt

Satish C Saripella

Ajay Srikrishna

George M Ansel

Jeffrey William Waldrip

Ping Wu

A circuit and method comprising a memory, a first latch, a second latch and a control circuit. The memory may be configured to write information in response to (i) an input data signal and (ii) an address signal. The first latch may be configured to hold the address in response to a control signal. The second latch may be configured to hold the data input signal in response to the control signal. The control circuit may be configured to present the control signal in response to (i) an enable signal and (ii) a detect signal.

Method, architecture and circuit for writing to and reading from a

A memory array having a physical depth of 2N-bits (N being an integer) includes control and data bus logic configured to control read and/or write operation in the memory array and to select the depth of the memory array. The control logic may include upper and lower byte control circuitry and the depth of the array may be selected from a group consisting of xN-bits and 2xN-bits, x being an integer. The control and data bus logic may be implemented as metal options within the device to be selected during fabrication to achieve a desired array depth.

Circuit and method for controlling memory depth

A reference voltage generator may include an input for receiving a first voltage for input to a sense amp. The reference voltage generator may also include an output for outputting a second voltage for input to the sense amp. The second voltage is influenced by the first voltage. Alternatively, a reference voltage generator may include a first input for receiving a first voltage on a first bitline. The reference voltage generator may also include a first output for outputting a second voltage on a second bitline. The second voltage is influenced by the first voltage. Alternatively, a reference voltage generator may include a first input for receiving a first voltage on a first transmission busline. The voltage generator may also include a first output for outputting a second voltage on a second transmission busline. The second voltage is influenced by the first voltage.

Reference voltage generator for reading a ROM cell in an integrated

A circuit and method comprising a memory, a first latch, a second latch and a control circuit. The memory may be configured to write information in response to (i) an input data signal and (ii) an address signal. The first latch may be configured to hold the address in response to a control signal. The second latch may be configured to hold the data input signal in response to the control signal. The control circuit may be configured to present the control signal in response to (i) a detect signal and (ii) a transition of the address signal.

Method, architecture and circuit for writing to a memory

A circuit comprising a sense amplifier, an evaluation circuit, a control circuit and a register circuit. The sense amplifier circuit may be configured to present a first output and a second output in response to (i) an input signal and (ii) an enable signal. The evaluation circuit may be configured to present an evaluation signal in response to the first and second outputs. The control circuit may be configured to present (i) a first clock signal, a second clock signal and an enable signal in response to (i) the evaluation signal and (ii) a wordline signal. The register circuit may be configured to hold either the first or second output in response to the first and second clock signals. The register circuit may be implemented as a master-slave register that may respond to the first and second clock signals.

Method, architecture and circuit for reducing and/or eliminating small

A memory device includes a random access memory (RAM) cell accessible through a RAM wordline and coupled between first and second bitlines; a read only memory (ROM) cell accessible through a ROM wordline and having an output coupled to the first bitline and an input configured to receive a first voltage signal; and a reference voltage generator having a first input coupled to the first bitline, a second input configured to receive the first voltage signal, and an output coupled to the second bitline. The memory device may further include a bitline load having an output coupled to the first bitline. A virtual ground driver configured to produce the first voltage signal may be coupled to the input of the read only memory cell. Further, column select pass gates configured to be under the control of a logic signal and having a first input coupled to the first bitline, a second input coupled to the second bitline, a first output and a second output may be provided. A sense amplifier having a first input coupled to the first output of the column select pass gates and a second input coupled to the second output of the column select pass gates may be included in the memory device. The memory device may be read by modulating a first voltage input to the sense amplifier using a second voltage input to the sense amplifier.

Read only/random access memory architecture and methods for operating

The present invention significantly lowers the continuous write cycle ICC, thus lowering the overall ICC specification, for multi-port (and single port) memory devices without significant changes in ICC.sub.WR and ICC.sub.RR currents. In one embodiment, a circuit for the generation of a Write Data select signal (i.e., TTL.sub.-- SEL) according to the present invention employs a unique 'write power-down' delay (t.sub.WPD) which is a function of 'CE+WE' (chip select and write enable) and incorporates the delay into the generation of the Write Data select signal, TTL.sub.-- SEL. The delay t.sub.WPD is provided by a delay device and is preferential. That is, a delay is provided when the internal write data select signal, i.e., TTL.sub.-- sel (which is a function of 'CE+WE'), transitions from logic '1' to a logic '0', but no delay is produced when TTL.sub.-- sel transitions from a logic '0' to a logic '1'.

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Starkville, MS, United States of America

Sudhaker Reddy Anumula