Ams Ag

Sudhakar Singamala

Ravi Kumar Adusumalli

Manfred Brandl

Rohit Ranganathan

Krishna Kanth Avalur

Vijay Ele

Chandra Nyshadham

Sandeep Vernekar

V Veeresh Babu

Veeresh Babu Vulligaddala

Andrzej Gajdardziew

Parvathy Sasikala Jayachandran Pillai

Vasanth Swaroop Yadagiri

A sensor arrangement for light sensing for light-to-frequency conversion. The sensor arrangement includes a photodiode, an analog-to-digital converter (ADC) operable to perform a chopping technique in response to a first clock signal (CLK), and convert a photocurrent (IPD) into a digital comparator output signal (LOUT). The ADC includes a sensor input coupled to the photodiode, an output for providing the digital comparator output signal (LOUT), an integrator including an integrator input coupled to the sensor input and operable to receive an integrator input signal, a first set of chopping switches coupled to a first amplifier, a second set of chopping switches electrically coupled to an output of the first amplifier and electrically coupled to input terminals of a second amplifier, and an integrator output providing an integrator output signal (OPOUT).

Sensor arrangement and method for dark count cancellation

An analog-to-digital converter () comprises a first and a second sampling capacitor (), a first integrator (), a first and a second input switch () coupling a first input terminal () and a common mode terminal () to a first electrode of the first sampling capacitor (), a third and a fourth input switch () coupling a second input terminal () and the common mode terminal () to a first electrode of the second sampling capacitor (), a fifth and a sixth input switch () coupling a second electrode of the first sampling capacitor () to an amplifier common mode terminal () and the first integrator input (), and a seventh and an eighth input switch () coupling a second electrode of the second sampling capacitor () to the amplifier common mode terminal () and the second integrator input ().

Analog-to-digital converter, measurement arrangement and method for analog-to-digital conversion

The invention relates to a cell balancing module, particularly for voltage balancing of a stack of batteries. The cell balancing module comprises an interface (SPI, VrefH, VrefL) to input a coded reference voltage (Vref) and input nodes (In, . . . , InN) for connecting a stack of energy storage cells (BAT, . . . , BATn). A switching unit (SW) is connected to each of the input nodes (In, . . . , InN) and a local balancing unit (loc) coupled to the switching unit (SW) and the interface (SPI, VrefH, VrefL). The local balancing unit (loc) is designed to compare the coded reference voltage (Vref) with cell voltages (VBAT, . . . , VBATn) of the stack of energy storage cells (BAT, . . . , BATn) to be connected and to charge balance the stack of energy storage cells (BAT, . . . , BATn) to be connected depending on the comparison of coded reference voltage (Vref) and cell voltages (VBAT, . . . , VBATn). The invention also relates to a voltage balancing device and method for cell balancing, particularly for voltage balancing of a stack of batteries.

Cell balancing module and method in voltage balancing device for a stack of batteries which compares the cell voltages to a coded reference voltage derived from at least two reference voltages

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Hyderabad Telangana, India

Sudhakar Singamala