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Matsushita Electric Industrial Co., Ltd.

Sudhakar Mannapuram Reddy

Wu-Tung Cheng

Nilanjan Mukherjee

Yu Jane Huang

Sadami Takeoka

Seiji Kajihara

Paul J Reuter

Yahya M Z Mustafa

Chien-Chung Tsai

Omer Ghazi Samman

Methods are described for scheduling the concurrent testing of multiple cores embedded in an integrated circuit. Test scheduling is performed by formulating the problem as a bin-packing problem and using a modified two-dimensional or three-dimensional bin-packing heuristic. The tests of multiple cores are represented as functions of at least the integrated circuit pins used to test the core and the core test time. The representations may include a third dimension of peak power required to test the core. The test schedule is represented as a bin having dimensions of at least integrated circuit pins and integrated circuit test time. The bin may include a third dimension of peak power. The scheduling of the multiple cores is accomplished by fitting the multiple core test representations into the bin.

Scheduling the concurrent testing of multiple cores embedded in an integrated circuit

A path under test is selected from a semiconductor integrated circuit that has been designed by a scan method. A test pattern is generated for the selected path so that the path is sensitized and a signal, passing through the path, changes its level at a time before or after a capture clock pulse is input to the circuit. Next, the test pattern generated is transformed into a normal scan pattern. Also, an expected output value, which should result from the test pattern input, is obtained. Then, the test pattern is input to the path under test and the resultant output value is compared to the expected value. In this manner, the path can be tested in such a manner as to see whether or not any hold error will occur.

Method for generating test pattern for semiconductor integrated circuit and method for testing semiconductor integrated circuit

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Iowa City, IA, United States of America

Sudhakar Mannapuram Reddy