Cadence Design Systems, Inc.

Sudeep Kumar Srivastava

Maayan Ziv

Kanwar Pal Singh

Nizar Hanna

Sanaa Halloun

Hanna Nizar

Tamer Mograbi

A method for a combined formal static analysis of a design code, the method comprising using a lint checker performing Lint checks to identify a suspected violation in the design code; using a formal static analyzer, performing formal checks to identify a suspected property that corresponds to the suspected violation; applying a formal proof technique to determine whether the suspected property is proven or disproved; and if the suspected property is disproved, issuing an alert.

Method and system for combined formal static analysis of a design code

The present disclosure relates to a method for use in a formal verification of an electronic design. Embodiments may include providing, using at least one processor, an electronic design and performing linting analysis using structural and formal methods of at least a portion of the electronic design. Embodiments may also include identifying a plurality of failures from the formal verification and identifying one or more of the plurality of failures as having a similar root cause. Embodiments may include grouping the one or more of the plurality of failures together, wherein grouping is based upon, at least in part, a check type.

System, method, and computer program product for grouping one or more failures in a formal verification

Growing community of inventors

Noida, India

Sudeep Kumar Srivastava