Intel Corporation

Sudarshanram Shetty

Travis T Schluessler

Subramaniam M Maiyuran

Guei-Yuan Lueh

Aravindh V Anantaraman

Chandra S Gurram

Vikranth Vemulapalli

Yoav Harel

Benjamin Pletcher

Shuai Mu

Carlos Nava Rodriguez

Ping Hang Cheung

PingHang Cheung

Srividya Karumuri

Bret Martin

Embodiments described herein are generally directed facilitating out-of-order execution of GPU texture sampler operations. An embodiment of a method includes a texture sampler of a GPU maintaining (i) a latency queue operable to store information regarding a set of transactions associated with each of multiple texture sampler operations and (ii) multiple virtual channel (VC) queues each operable to store information regarding transactions for a respective single texture sampler operation at a time. Out-of-order processing of the texture sampler operations is facilitated by making use of the latency queue and the VC queues. For example, during a transaction processing interval, the availability of data in a cache for the transactions associated with each of the VC queues may be determined. A VC queue may be selected based on the determined availability of data. A transaction associated with a head of the selected VC queue may then be processed.

Out-of-order execution of graphics processing unit texture sampler operations

A graphics processing apparatus includes a graphics processor and a constant cache. The graphics processor has a number of execution instances that will generate requests for constant data from the constant cache. The constant cache stores constants of multiple constant types. The constant cache has a single level of hierarchy to store the constant data. The constant cache has a banking structure based on the number of execution instances, where the execution instances generate requests for the constant data with unified messaging that is the same for the different types of constant data.

High performance constant cache and constant access mechanisms

An apparatus to facilitate dynamic cache control is disclosed. The apparatus includes one or more processors to profile execution characteristics of a graphics workload at a processing resource to generate profile data indicating a quantity of cache hits that occur at a cache memory and apply one or more cache settings to the cache memory based on the profile data.

Dynamic cache control mechanism

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Portland, OR, United States of America

Sudarshanram Shetty