Shaoxing Yuanfang Semiconductor Co., Ltd.

Aura Semicoductor Pvt. Ltd

Sudarshan Varadarajan

Raja Prabhu J

Debasish Behera

Girisha Angadi Basavaraja

Nandakishore Palla

Manikanta Sakalabhaktula

Shyam Somayajula

Arnold J D'Souza

Chandrashekar Bg

Chandrasekhar Bg

A time-to-digital converter (TDC) includes a counter and a digital core. The counter is designed to generate a sequence of counts representing a number of transitions of interest of a first clock signal. The counter includes an asynchronous circuit and a synchronous circuit to respectively generate a first set of bits and a second set of bits of each of the sequence of numbers. The digital core is designed to process a pair of counts of the sequence.

Counter design for a time-to-digital converter (TDC)

A time-to-digital converter (TDC) includes a count logic and a digital core. The count logic generates a first sequence of counts representing a first sequence of edges of a first periodic signal, and a second sequence of counts representing a second sequence of edges of a second periodic signal. The digital core generates a sequence of outputs representing the phase differences between the first periodic signal and the second periodic signal from the first sequence of counts and the second sequence of counts. Each output is generated from a pair of successive edges of the first direction of one of the periodic signals and an individual one of the other periodic signal occurring between the pair, and the output is set equal to the minimum of difference of the individual one with the first value of the pair and the individual one with the second value of the pair.

Time-to-digital converter (TDC) measuring phase difference between periodic inputs

A charge pump includes a scaler circuit and a selector circuit. The scaler circuit is designed to scale an intermediate voltage by a scaling factor to generate a scaled voltage. The selector circuit is designed to select and provide the intermediate voltage from multiple voltages. The selector circuit includes a comparator block to generate a select signal indicating which of the multiple voltages has the highest magnitude. The selector circuit includes multiple switches, each switch to receive a respective voltage from among the multiple voltages and pass the corresponding voltage as the intermediate voltage if the select signal indicates that the voltage received by the corresponding switch has the highest magnitude.

Charge pump for scaling the highest of multiple voltages when at least one of the multiple voltages varies

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Bengaluru, India

Sudarshan Varadarajan