Analog Devices Global Unlimited Company

Analog Devices Global

Sudarshan Onkar

Michael William O'Brien

Kenneth J Mulvaney

Philip P E Quinlan

Joshua J Nekl

Aspects of this disclosure relate to detecting a header of a packet. A receive signal path can provide a receive signal that includes packets and a guard preamble between successive packets of the packets. A receiver control circuit can trigger a timer that sets a time for detecting a header of a packet in response to detecting an end of a preamble of the packet.

Multi-packet protocol header detection

Aspects of this disclosure relate to transmitting and/or receiving a frequency-shift keying signal including a packet that includes a preamble and a payload. The preamble has a first modulation index that has a smaller magnitude than a second modulation index of the payload. This can enhance frequency correction in a receive device that receives the packet.

Modulation index adjustment

In a communication receiver circuit, an amplifier circuit can include an adjustable gain. A signal corresponding to a portion of a transmitted frame can be received, and a gain of the receiver circuit can be adjusted such as automatically, and such adjustment can be referred to as automatic gain control (AGC). An offset correction can be performed to adjust for an error in a received representation of a transmitted carrier, and such offset correction can be referred to as carrier frequency offset (CFO) correction. A portion of the received signal can be dynamically allocated between AGC and CFO correction, such as allocating a longer duration to CFO correction when AGC results in a relatively higher receiver gain, and allocating a shorter duration to CFO correction when AGC results in a relatively lower receiver gain.

Automatic gain control (AGC) assisted carrier offset correction

Embodiments of the present disclosure provide a digital filter module for use in receivers, particularly suitable for use in a narrow-band electromagnetic receiver. Design of the module is based on a recognition that providing to the module samples of a signal received by a receiver and sampled at a sampling frequency equal to four times the intermediate frequency of the receiver, eliminating zeros in the filter, and implementing the filter module as a resource-shared second-order filter structure that includes two sections advantageously enables saving some hardware components, particularly some multipliers and adders, in implementing a versatile digital filter module that can function either as two real filters or one complex filter. In this manner, substantial reduction of area and power consumption of the filter module may be achieved, while maintaining sufficiently high filtering performance.

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Bengaluru, India

Sudarshan Onkar